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A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm

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Reconfigurable Computing: Architectures, Tools and Applications (ARC 2007)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 4419))

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Abstract

In this contribution, we derive a novel parallel formulation of the standard Itoh-Tsujii algorithm for multiplicative inverse computation over GF(2m). When implemented in a Virtex 3200E FPGA device, our design is able to compute multiplicative inversion over GF(2193) after 20 clock cycles in about 0.94 μS.

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References

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Authors and Affiliations

  1. Computer Science Department, Centro de Investigación y de Estudios Avanzados del IPN, Av. Instituto Politécnico Nacional No. 2508, México D.F.,  

    Francisco Rodríguez-Henríquez, Guillermo Morales-Luna & Nareli Cruz-Cortés

  2. Centre for Cyber Technology and Spectrum Management, (CCT & SM), NUST, Islamabad, Pakistan

    Nazar A. Saqib

Authors
  1. Francisco Rodríguez-Henríquez
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  2. Guillermo Morales-Luna
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  3. Nazar A. Saqib
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  4. Nareli Cruz-Cortés
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Editor information

Pedro C. Diniz Eduardo Marques Koen Bertels Marcio Merino Fernandes João M. P. Cardoso

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© 2007 Springer Berlin Heidelberg

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Rodríguez-Henríquez, F., Morales-Luna, G., Saqib, N.A., Cruz-Cortés, N. (2007). A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_21

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  • DOI: https://doi.org/10.1007/978-3-540-71431-6_21

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-71430-9

  • Online ISBN: 978-3-540-71431-6

  • eBook Packages: Computer ScienceComputer Science (R0)

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