Abstract
In this paper we present a clock frequency watch dog that can be realized using a digital standard CMOS library. Such watch dog is required to prevent clock speed manipulations that can support side channel attacks on cryptographic hardware devices. The additional area and power consumed by the watch dog for an AES hardware accelerator are 4,200μm2 and 2nJ per 128 bit respectively. The physical properties and the use of standard CMOS technology ensure extremely low additional production cost. Thus, our approach is very well suited to improve the security of low cost devices such as wireless sensor nodes.
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Keywords
- Wireless Sensor Network
- Clock Frequency
- Advance Encryption Standard
- Side Channel Attack
- High Clock Frequency
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Vater, F., Peter, S., Langendörfer, P. (2007). Combinatorial Logic Circuitry as Means to Protect Low Cost Devices Against Side Channel Attacks. In: Sauveron, D., Markantonakis, K., Bilas, A., Quisquater, JJ. (eds) Information Security Theory and Practices. Smart Cards, Mobile and Ubiquitous Computing Systems. WISTP 2007. Lecture Notes in Computer Science, vol 4462. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72354-7_20
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DOI: https://doi.org/10.1007/978-3-540-72354-7_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-72353-0
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