Abstract
Formal and semi-formal verification of analog/mixed-signal circuits is complicated by the difficulty of obtaining circuit models suitable for analysis. We propose a method to generate a formal model from simulation traces. The resulting model is conservative in that it includes all of the original simulation traces used to generate it plus additional behavior. Information obtained during the model generation process can also be used to refine the simulation and verification process.
Support from SRC contract 2005-TJ-1357 and an SRC Graduate Fellowship.
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Little, S., Walter, D., Jones, K., Myers, C. (2007). Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. In: Namjoshi, K.S., Yoneda, T., Higashino, T., Okamura, Y. (eds) Automated Technology for Verification and Analysis. ATVA 2007. Lecture Notes in Computer Science, vol 4762. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-75596-8_10
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DOI: https://doi.org/10.1007/978-3-540-75596-8_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-75595-1
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