Abstract
This paper introduces a low cost near-field mapping system. This system scans automatically and dynamically, in the time domain, the magnetic field emitted by integrated circuits during the execution of a repetitive set of instructions. Application of this measurement system is given to an industrial chip designed with a 180nm CMOS process. This application demonstrates the efficiency of the system but also the helpfulness of the results obtained to identify paths followed by the current, enabling to locate the potential IR drop zones.
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© 2009 Springer-Verlag Berlin Heidelberg
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Ordas, T., Lisart, M., Sicard, E., Maurine, P., Torres, L. (2009). Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_23
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DOI: https://doi.org/10.1007/978-3-540-95948-9_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-95947-2
Online ISBN: 978-3-540-95948-9
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