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Reconfigurable Computing: Architectures, Tools and Applications

5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009, Proceedings

  • Conference proceedings
  • © 2009

Overview

Editors:
  1. Jürgen Becker

    1. Institut für Technik der Informationsverarbeitung (ITIV), Universität Karlsruhe (TH), Karlsruhe, Germany

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  2. Roger Woods

    1. ECIT Institute, Queen’s University Belfast, Belfast, UK

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  3. Peter Athanas

    1. Bradley Department of Electrical and Electronic Engineering, Virginia Tech, Blacksburg, USA

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  4. Fearghal Morgan

    1. Department of Electronic Engineering, National University of Ireland, Galway, Ireland

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 5453)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: ARC 2009.

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About this book

This book constitutes the refereed proceedings of the 5th International Workshop on Applied Reconfigurable Computing, ARC 2009, held in Karlsruhe, Germany, in March 2009. The 21 full papers and 21 short papers presented together with the abstracts of 3 keynote lectures were carefully reviewed and selected from about 100 submissions. The papers are organized in topical sections on FPGA security and bitstream analysis, fault tolerant systems, architectures, place and route techniques, cryptography, and resource allocation and scheduling, as well as on applications.

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Table of contents (45 papers)

  1. Front Matter

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  3. Applications 1

    1. A HyperTransport 3 Physical Layer Interface for FPGAs

      • Heiner Litz, Holger Froening, Ulrich Bruening
      Pages 4-14

    2. Parametric Design for Reconfigurable Software-Defined Radio

      • Tobias Becker, Wayne Luk, Peter Y. K. Cheung
      Pages 15-26

  4. Applications 2

    1. Hardware/Software FPGA Architecture for Robotics Applications

      • Juan Carlos Moctezuma Eugenio, Miguel Arias Estrada
      Pages 27-38

    2. Reconfigurable Operator Based Multimedia Embedded Processor

      • Daniel Menard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant et al.
      Pages 39-49

  5. FPGA Security and Bitstream Analysis

    1. A Protocol for Secure Remote Updates of FPGA Configurations

      • Saar Drimer, Markus G. Kuhn
      Pages 50-61

    2. FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing

      • Krzysztof Kępa, Fearghal Morgan, Krzysztof Kościuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker
      Pages 62-73

  6. Fault Tolerant Systems

    1. An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

      • Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
      Pages 74-84

    2. Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs

      • Luca Sterpone
      Pages 85-96

  7. Architectures

    1. A Novel Local Interconnect Architecture for Variable Grain Logic Cell

      • Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
      Pages 97-109

    2. Dynamically Adapted Low Power ASIPs

      • Mateus B. Rutzig, Antonio Carlos S. Beck, Luigi Carro
      Pages 110-122

    3. Fast Optical Reconfiguration of a Nine-Context DORGA

      • Mao Nakajima, Minoru Watanabe
      Pages 123-132

  8. Place and Route Techniques

    1. Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep

      • Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung
      Pages 133-144

    2. On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks

      • Ricardo Ferreira, Alex Damiany, Julio Vendramini, Tiago Teixeira, João M. P. Cardoso
      Pages 145-156

    3. A New Datapath Merging Method for Reconfigurable System

      • Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini
      Pages 157-168

  9. Cryptography

    1. Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform

      • Xu Guo, Patrick Schaumont
      Pages 169-180

    2. Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm

      • Jaeyoung Yi, Karam Park, Joonseok Park, Won W. Ro
      Pages 181-192
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Other volumes

  1. Reconfigurable Computing: Architectures, Tools and Applications

Editors and Affiliations

  • Institut für Technik der Informationsverarbeitung (ITIV), Universität Karlsruhe (TH), Karlsruhe, Germany

    Jürgen Becker

  • ECIT Institute, Queen’s University Belfast, Belfast, UK

    Roger Woods

  • Bradley Department of Electrical and Electronic Engineering, Virginia Tech, Blacksburg, USA

    Peter Athanas

  • Department of Electronic Engineering, National University of Ireland, Galway, Ireland

    Fearghal Morgan

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