Abstract
Two main components in AES-GCM (Advanced Encryption Standard with Galois Counter Mode) are an AES engine and a finite field multiplier over GF(2128) in the universal hashing function (GHASH). Because of the inherent computation feedback, the system performance is usually determined by the finite field multiplier based on the known FPGA implementations to date. In this paper, we present the throughput optimization of AES-GCM with a 4-stage pipelined finite field multiplier based on Karatsuba-Ofman algorithm on FPGAs. The critical delay of the pipelined multiplier then matches that of the AES implementation with either the BlockRAM SubBytes, pipelined composite field SubBytes or LUT-based SubBytes. The AES-GCM throughput reaches more than 30Gbps on a single Xilinx Virtex Chip. The experimental results show that we achieve the most efficient AES-GCM implementations on FPGAs to date.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
McGrew, D.A., Viega, J.: The Galois/Counter Mode of Operation (GCM). Updated submission to NIST, Modes of Operation Process (May 2005)
NIST, Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC. NIST Special Publication 800-38D (November 2007)
NIST, Advanced Encryption Standard (AES). FIPS Publication 197 (November 26, 2001)
Viega, J., McGrew, D.: The Use of Galois/Counter Mode (GCM) in IPsec Encapsulating Security Payload. RFC 4106 (2005)
McGrew, D., Viega, J.: The Use of Galois Message Authentication Code (GMAC) in IPsec ESP and AH. RFC 4543 (2006)
IEEE, 802.1AE - Media Access Control (MAC) Security (2006)
IEEE, P1619.1, Standard for Authenticated Encryption with Length Expansion for Storage Devices (2006)
INCITS, Fibre Channel Security Protocols, REC 1.74 (2006)
Jaervinen, K.U., Tommiska, M.T., Skyttae, J.O.: A Fully Pipelined Memoryless 17.8Gbps AES-128 Encrypto. FPGA (2003)
Standaert, F.-X., Rouvroy, G., Quisquater, J.-J., Legat, J.-D.: Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 334–350. Springer, Heidelberg (2003)
Zhang, X., Parhi, K.K.: High-Speed VLSI Architectures for the AES Algorithm. IEEE Transaction on VLSI 12(9), 957–967 (2004)
Good, T., Benaissa, M.: AES on FPGA: from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 427–440. Springer, Heidelberg (2005)
Bulens, P., Standaert, F.-X., Quisquater, J.-J., Pellegrin, P., Rouvroy, G.: Implementation of the AES-128 on Virtex-5 FPGAs. In: Vaudenay, S. (ed.) AFRICACRYPT 2008. LNCS, vol. 5023, pp. 16–26. Springer, Heidelberg (2008)
Lemsitzer, S., Wolkerstorfer, J., Felber, N., Braendli, M.: Multi-gigabit GCM-AES Architecture Optimized for FPGAs. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 227–238. Springer, Heidelberg (2007)
Zhou, G., Michalik, H., Hinsenkamp, L.: Efficient and High-Throughput Implementations of AES-GCM on FPGAs. In: Proceedings of International Conference on Field Programmable Technology, ICFPT 2007, pp. 185–192 (December 2007)
Satoh, A., Sugawara, T., Aoki, T.: High-speed Pipelined Hardware architecture for Galois Counter Mode. In: Garay, J.A., Lenstra, A.K., Mambo, M., Peralta, R. (eds.) ISC 2007. LNCS, vol. 4779, pp. 118–129. Springer, Heidelberg (2007)
Satoh, A.: High-speed hardware architectures for authenticated encryption mode GCM. In: Proceedings IEEE International Symposium on Circuits and Systems (ISCAS) (May 2006)
Xilinx, Virtex-4 User Guide, V2.3 (August 2007), http://www.xilinx.com
Xilinx, Virtex-5 User Guide, V3.3 (Feburary 2008), http://www.xilinx.com
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Zhou, G., Michalik, H., Hinsenkamp, L. (2009). Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. In: Becker, J., Woods, R., Athanas, P., Morgan, F. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2009. Lecture Notes in Computer Science, vol 5453. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00641-8_20
Download citation
DOI: https://doi.org/10.1007/978-3-642-00641-8_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00640-1
Online ISBN: 978-3-642-00641-8
eBook Packages: Computer ScienceComputer Science (R0)