Abstract
Minimizing power consumption continues to grow as a critical design issue for many platforms, from embedded systems to CMPs to ultrascale parallel systems. As growing cache sizes consume larger portions of the die, reducing their power consumption becomes increasingly important. Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We introduce a reuse distance (RD) drowsy caching mechanism that exploits temporal locality, delivers equivalent or better energy savings than the best policies from the literature, suffers little performance overhead, is simple to implement, and scales with cache size and hierarchy depth.
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Bhadauria, M., McKee, S.A., Singh, K., Tyson, G.S. (2009). Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers II. Lecture Notes in Computer Science, vol 5470. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00904-4_5
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DOI: https://doi.org/10.1007/978-3-642-00904-4_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00903-7
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