Abstract
A novel hardware architecture of the competitive learning (CL) algorithm with k-winners-take-all activation is presented in this paper. It is used as a custom logic block in the arithmetic logic unit (ALU) of the softcore NIOS processor for CL training. Both the partial distance search (PDS) module and hardware divider adopt finite precision calculation for area cost reduction at the expense of slight degradation in training performance. The PDS module also employs subspace search and multiple-coefficient accumulation techniques for effective reduction of the computation latency for the PDS search. Experiment results show that the CPU time is lower than that of Pentium IV processors running the CL training program without the support of custom hardware.
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References
NIOS II Processor Reference Handbook (2008), Altera Corporation, http://www.altera.com/literature/lit-nio2.jsp
Gersho, A., Gray, R.M.: Vector Quantization and Signal Compression. Kluwer, Norwood (1992)
Hauck, S., Dehon, A.: Reconfigurable Computing. Morgan Kaufmann, San Francisco (2008)
Haykin, S.: Neural Networks: A Comprehensive Foundation, 2nd edn. Prentice Hall, Englewood Cliffs (1998)
Hwang, W.J., Lin, F.J., Zeng, Y.C.: Fast Design Algorithm for Competitive Learning. Electronics Letters, 1469–1470 (1997)
Kohonen, T.: The self-organizing map, 3rd edn. Springer, Heidelberg (2000)
Theodoridis, S., Koutroumbas, K.: Pattern Recognition, 3rd edn. Academic Press, London (2006)
Walnut, D.F.: An Introduction to Wavelet Analysis. Birkhauser, Basel (2002)
Wang, C.L., Chen, L.M.: A New VLSI Architecture for Full-Search Vector Quantization. IEEE Trans. Circuits and Systems for Video Technology, 389–398 (1996)
Yen, J.C., Guo, J.I., Chen, H.C.: A new k-winners-take-all neural network and its array architecture. IEEE Trans. Neural Networks, 901–912 (1998)
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© 2009 Springer-Verlag Berlin Heidelberg
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Li, HY., Yeh, YJ., Hwang, WJ., Yang, CT. (2009). High Speed k-Winner-Take-ALL Competitive Learning in Reconfigurable Hardware. In: Chien, BC., Hong, TP., Chen, SM., Ali, M. (eds) Next-Generation Applied Intelligence. IEA/AIE 2009. Lecture Notes in Computer Science(), vol 5579. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-02568-6_60
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DOI: https://doi.org/10.1007/978-3-642-02568-6_60
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-02567-9
Online ISBN: 978-3-642-02568-6
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