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Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays

  • Conference paper
High Performance Embedded Architectures and Compilers (HiPEAC 2010)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5952))

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Abstract

Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10-100 MOps/mW of power efficiency and are software programmable. However, this cardinal promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions have greatly improved the computation speed, they have largely ignored the impact of the local memory architecture on the achievable power and performance. This paper motivates the need for memory-aware application mapping for CGRAs, and proposes an effective solution for application mapping that considers the effects of various memory architecture parameters including the number of banks, local memory size, and the communication bandwidth between the local memory and the external main memory. Our proposed solution achieves 62% reduction in the energy-delay product, which factors into about 47% and 28% reduction in the energy consumption and runtime, respectively, as compared to memory-unaware mapping for realistic local memory architectures. We also show that our scheme scales across a range of applications, and memory parameters.

This work was supported by the Korea Science and Engineering Foundation(KOSEF) NRL Program grant funded by the Korea government(MEST) (No. 2009-0083190), the Engineering Research Center of Excellence Program of Korea Ministry of Education, Science and Technology(MEST)/ Korea Science and Engineering Foundation(KOSEF) (R11-2008-007-01001-0), Seoul R&BD Program(10560), the Korea Research Foundation Grant funded by the Korean Government(MOEHRD) (KRF-2007-357-D00225), 2009 Research Fund of the UNIST (Ulsan National Institute of Science and Technology), and grants from Raytheon, Stardust foundation, and NSF (grant no. 0916652).

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Author information

Authors and Affiliations

  1. School of EECS, Seoul National University, Seoul, Korea

    Yongjoo Kim, Jonghee Yoon & Yunheung Paek

  2. School of ECE, Ulsan National Institute of Science and Technology, Ulsan, Korea

    Jongeun Lee

  3. Compiler Microarchitecture Lab, Arizona State University, USA

    Aviral Shrivastava

Authors
  1. Yongjoo Kim
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  2. Jongeun Lee
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  3. Aviral Shrivastava
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  4. Jonghee Yoon
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  5. Yunheung Paek
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Editor information

Editors and Affiliations

  1. Department of Electrical and Computer Engineering, The University of Texas at Austin, 1 University Station C0803, TX 78712-0240, Austin, USA

    Yale N. Patt

  2. Dipartimento di Ingegneria della Informazione, Università di Pisa, Via Diotisalvi 2, 56100, Pisa, Italy

    Pierfrancesco Foglia

  3. IBM T.J.Watson Research Center, 19 Skyline Drive, NY 10532, Hawthorne, USA

    Evelyn Duesterwald

  4. Hewlett-Packard, Cami de Can Graells 1-21, Sant Cugat del Vallés, 08174, Barcelona, Spain

    Paolo Faraboschi

  5. Computer Architecture Department, Technical University of Catalunya (UPC), c/Jordi Girona 1-3, 08034, Barcelona, Spain

    Xavier Martorell

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© 2010 Springer-Verlag Berlin Heidelberg

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Kim, Y., Lee, J., Shrivastava, A., Yoon, J., Paek, Y. (2010). Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays. In: Patt, Y.N., Foglia, P., Duesterwald, E., Faraboschi, P., Martorell, X. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2010. Lecture Notes in Computer Science, vol 5952. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11515-8_14

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  • DOI: https://doi.org/10.1007/978-3-642-11515-8_14

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-11514-1

  • Online ISBN: 978-3-642-11515-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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