Abstract
It is evident that most new computing platforms are becoming more and more complex encapsulating multiple cores and reconfigurable elements. This offers the designers a multitude of resources. It is their responsibility to exploit the available resources in such a way to efficiently implement their applications. Furthermore, the complexity of the applications that run on such platforms is increasing as well. Applications running on such platforms need to cope with dynamic events and have their resource requirements vary during the execution time. In order to cope with this dynamism applications rely in the usage of dynamic data. Applications use containers such as dynamic data types in order to store and retrieve these dynamic data. In this work a set of methodologies that is able to optimize the containers holding the dynamic data and efficiently assign them on the available memory resources is presented. The proposed approach is evaluated in a scheduler for an IEEE802.16-based broadband wireless telecom system and a 3D game application, achieving reductions in the memory energy consumption of 32% and 51% respectively.
This work is partially supported by E.C. funded MORPHEUS IST-4-02734 Project, www.morpheus-ist.org
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Thoma, F., Kuhnle, M., Bonnot, P., Panainte, E., Bertels, K., Goller, S., Schneider, A., Guyetant, S., Schuler, E., Muller-Glaser, K., Becker, J.: Morpheus: Heterogeneous reconfigurable computing. In: Proc. of FPL, August 2007, pp. 409–414 (2007)
Marwedel, P., Wehmeyer, L., Verma, M., Steinke, S., Helmig, U.: Fast, predictable and low energy memory references through architecture-aware compilation. In: Proc. of ASP-DAC, pp. 4–11 (2004)
Atienza, D., Mamagkakis, S., Catthoor, F., Mendias, J.M., Soudris, D.: Dynamic memory management design methodology for reduced memory footprint in multimedia and wireless network applications. In: Proc. of DATE (2004)
Antonakos, J., Mansfield, K.: Practical data structures using C/C++. Prentice-Hall, Englewood Cliffs (1999)
Wood, D.: Data structures, algorithms, and performance. Addison-Wesley Longman Publishing Co., Inc., Amsterdam (1993)
Daylight, E., Atienza, D., Vandecappelle, A., Catthoor, F., Mendias, J.: Memory-access-aware data structure transformations for embedded software with dynamic data accesses. IEEE TVLSI 12(3), 269–280 (2004)
Bartzas, A., Mamagkakis, S., Pouiklis, G., Atienza, D., Catthoor, F., Soudris, D., Thanailakis, A.: Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. In: Proc. of DATE (March 2006)
Papadopoulos, L., Baloukas, C., Zompakis, N., Soudris, D.: Systematic data structure exploration of multimedia and network applications realized embedded systems. In: Proc. of IC-SAMOS 2007, July 2007, pp. 58–65 (2007)
Palermo, D.J., Banerjee, P.: Automatic selection of dynamic data partitioning schemes for distributed-memory multicomputers. In: Sehr, D., Banerjee, U., Gelernter, D., Nicolau, A., Padua, D.A. (eds.) LCPC 1996. LNCS, vol. 1239, pp. 392–406. Springer, Heidelberg (1997)
Dominguez, A., Udayakumaran, S., Barua, R.: Heap Data Allocation to Scratch-Pad Memory in Embedded Systems. Journal of Embedded Computing (2005)
Kandemir, M., Kadayif, I., Choudhary, A., Ramanujam, J., Kolcu, I.: Compiler-directed scratch pad memory optimization for embedded multiprocessors. IEEE TVLSI 12, 281–287 (2004)
Verma, M., Steinke, S., Marwedel, P.: Data partitioning for maximal scratchpad usage. In: Proc. of ASP-DAC, pp. 77–83. ACM Press, New York (2003)
Verma, M., Wehmeyer, L., Marwedel, P.: Cache-aware scratchpad allocation algorithm. In: Proc. of DATE (2004)
Udayakumaran, S., Dominguez, A., Barua, R.: Dynamic allocation for scratch-pad memory using compile-time decisions. Trans. on Embedded Computing Sys. 5(2), 472–511 (2006)
Panda, P.R., Dutt, N.D., Nicolau, A.: On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Trans. Des. Autom. Electron. Syst. 5(3), 682–704 (2000)
Benini, L., de Micheli, G.: System-level power optimization: techniques and tools. ACM Trans. Des. Autom. Electron. Syst. 5(2), 115–192 (2000)
Khuri, S., Bäck, T., Heitkötter, J.: The zero/one multiple knapsack problem and genetic algorithms. In: Proc. of SAC, pp. 188–193. ACM, New York (1994)
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Bartzas, A., Baloukas, C., Soudris, D., Potamianos, K., Ieromnimon, F., Voros, N.S. (2010). Dynamic Data Type Optimization and Memory Assignment Methodologies. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_22
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DOI: https://doi.org/10.1007/978-3-642-11802-9_22
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