Abstract
This paper presents the design and FPGA-implementation of a sampler that is suited for sampling real-time events in embedded systems. Such sampling is useful, for example, to test whether real-time events are handled in time on such systems. By designing and implementing the sampler as a logic analyzer on an FPGA, several design parameters can be explored and easily modified to match the behavior of different kinds of embedded systems. Moreover, the trade-off between price and performance becomes easy, as it mainly exists of choosing the appropriate type and speed grade of an FPGA family.
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Penneman, N., Perneel, L., Timmerman, M., De Sutter, B. (2010). An FPGA-Based Real-Time Event Sampler. In: Sirisuk, P., Morgan, F., El-Ghazawi, T., Amano, H. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2010. Lecture Notes in Computer Science, vol 5992. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12133-3_35
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DOI: https://doi.org/10.1007/978-3-642-12133-3_35
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-12132-6
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