Abstract
Nowadays, majority of applications struggle to achieve good behavior of their subsystems by cooperation of systems, which is independently designed, separately located, but mutually affecting subsystems. Such coordinating systems are hard to attain the specific structural models and effective parameters. In such cases, the evolved hardware (EHW) methods with evolutionary Algorithms (EA) to achieve sophisticated level of information [2]. Numeral systems were introduced with evolvable hardware on a single chip to overcome the lack of flexibility, with the support of modifiable evolutionary algorithm stored in software on a built-in processor. This paper proposed the architecture with Xilinx Virtex-II Pro FPGA with interfaced PowerPC processor. Due to this speedy processing, time consumption in hardware and also allows other parts to be easily modifiable software. The proposed technique will provide more benefits in the future work as regards cost and compactness [1]. The system was completely analyzed on physical devices with software executing in parallel with fitness computation in digital logic circuits, and the results determine that the system uses only double the time when compared to a PC running at 10 times faster clock speed[6].
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Anandaraj, S.P., Kumar, R.N., Ravi, S., Sharma, S.S.V.N. (2010). Fault Tolerant Implementation of Xilinx Vertex FPGA for Sensor Systems through On-Chip System Evolution. In: Kim, Th., Vasilakos, T., Sakurai, K., Xiao, Y., Zhao, G., Ślęzak, D. (eds) Communication and Networking. FGCN 2010. Communications in Computer and Information Science, vol 120. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17604-3_53
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DOI: https://doi.org/10.1007/978-3-642-17604-3_53
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