Abstract
Cache partitioning and power-gating schemes are major research topics to achieve a high-performance and low-power shared cache for next generation chip multiprocessors(CMPs). We propose a poweraware cache partitioning mechanism, which is a scheme to realize both low power and high performance using power-gating and cache partitioning at the same time. The proposed cache mechanism is composed of a way-allocation function and power control function; each function works based on the cache locality assessment. The performance evaluation results show that the proposed cache mechanism with a performanceoriented parameter setting can reduce energy consumption by 20% while keeping the performance, and the mechanism with an energy-oriented parameter setting can reduce 54% energy consumption with a performance degradation of 13%. The hardware implementation results indicate that the delay and area overheads to control the proposed mechanism are negligible, and therefore hardly affect both the entire chip design and performance.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Wall, D.W.: Limits of instruction-level parallelism. SIGARCH Comput. Archit. News 19(2), 176–188 (1991)
Nayfeh, B., Olukotun, K.: A single-chip multiprocessor. Computer 30(9), 79–85 (1997)
Suh, G.E., Rudolph, L., Devadas, S.: Dynamic partitioning of shared cache memory. Journal of Supercomputing 28(1), 7–26 (2004)
Chandra, D., Guo, F., Kim, S., Solihin, Y.: Predicting inter-thread cache contention on a chip multi-processor architecture. In: HPCA 2005: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, Washington, DC, USA, pp. 340–351. IEEE Computer Society, Los Alamitos (2005)
Kim, S., Chandra, D., Solihin, Y.: Fair cache sharing and partitioning in a chip multiprocessor architecture. In: PACT 2004: the 13th International Conference on Parallel Architectures and Compilation Techniques, Washington, DC, USA, pp. 111–122. IEEE Computer Society, Los Alamitos (2004)
Qureshi, M.K., Patt, Y.N.: Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In: MICRO 39: the 39th Annual IEEE/ACM International Symposium on Microarchitecture, Washington, DC, USA, pp. 423–432. IEEE Computer Society, Los Alamitos (2006)
Butts, J.A., Sohi, G.: A static power model for architects. In: MICRO-33: 33rd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 191–201 (2000)
Kim, N., Austin, T., Blaauw, D., Mudge, T., Flautner, K., Hu, J., Irwin, M., Kandemir, M., Narayanan, V.: Leakage current: Moore’s law meets static power. Computer 36(12), 68–75 (2003)
International technology roadmap for semiconductors, http://public.itrs.net
Meng, Y., Sherwood, T., Kastner, R.: Exploring the limits of leakage power reduction in caches. ACM Trans. Archit. Code Optim. 2(3), 221–246 (2005)
Stan, M., Skadron, K.: Power-aware computing. Computer 36(12), 35–38 (2003)
Albonesi, D.: Selective cache ways: on-demand cache resource allocation. In: MICRO-32: 32nd Annual International Symposium on Microarchitecture, pp. 248–259 (November 1999)
Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, N.: Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9(1), 77–89 (2001)
Powell, M., Yang, S.H., Falsafi, B., Roy, K., Vijaykumar, T.N.: Gated-vdd: a circuit technique to reduce leakage in deep-submicron cache memories. In: ISLPED 2000: The 2000 International Symposium on Low Power Electronics and Design, pp. 90–95. ACM, New York (2000)
Kaxiras, S., Hu, Z., Martonosi, M.: Cache decay: exploiting generational behavior to reduce cache leakage power. In: 28th Annual International Symposium on Computer Architecture, June 30-July 4, pp. 240–251 (2001)
Flautner, K., Kim, N.S., Martin, S., Blaauw, D., Mudge, T.: Drowsy caches: simple techniques for reducing leakage power. In: 29th Annual International Symposium on Computer Architecture, May 25-29, pp. 148–157 (2002)
Kobayashi, H., Kotera, I., Takizawa, H.: Locality analysis to control dynamically way-adaptable caches. SIGARCH Comput. Archit. News 33(3), 25–32 (2005)
Binkert, N., Dreslinski, R., Hsu, L., Lim, K., Saidi, A., Reinhardt, S.: The m5 simulator: Modeling networked systems. IEEE Micro 26(4), 52–60 (2006)
Wilton, S., Jouppi, N.: Cacti: an enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits 31(5), 677–688 (1996)
The Standard Performance Evaluation Corporation, http://www.spec.org/
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Kotera, I., Abe, K., Egawa, R., Takizawa, H., Kobayashi, H. (2011). Power-Aware Dynamic Cache Partitioning for CMPs. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers III. Lecture Notes in Computer Science, vol 6590. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19448-1_8
Download citation
DOI: https://doi.org/10.1007/978-3-642-19448-1_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19447-4
Online ISBN: 978-3-642-19448-1
eBook Packages: Computer ScienceComputer Science (R0)