Abstract
Hardware complexity of a root-raised-cosine (RRC) pulse shaping filter is dominated by the number of binary multiplications. In this paper an efficient multiplication scheme has been used to implement an RRC matched filter for Digital Video Broadcasting-Second Generation (DVB-S2) specifications. Nibble processing of the filter coefficients is performed to achieve computational efficiency. Quantization of the filter coefficient is used as a trade-off for the filter design. Twelve-bit quantized coefficients are used to obtain low hardware cost with satisfactory filter performance. Matlab simulation is used to compare and contrast the performance of an RRC filter with that of a standard floating point design. Hardware of the filter is simulated and synthesized using Xilinx ISE10.1. Implementation results show a 25% savings in LUT count. The use of nibble processing has the potential to reduce the hardware complexity of an RRC filter and is also applicable to other DVBS2 receiver schemes.
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© 2011 Springer-Verlag Berlin Heidelberg
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Agarwal, V., Kim, P., Oh, DG., Ahn, DS. (2011). Hardware Efficient Root-Raised-Cosine Pulse Shaping Filter for DVB-S2 Receivers. In: Abraham, A., Lloret Mauri, J., Buford, J.F., Suzuki, J., Thampi, S.M. (eds) Advances in Computing and Communications. ACC 2011. Communications in Computer and Information Science, vol 191. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22714-1_61
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DOI: https://doi.org/10.1007/978-3-642-22714-1_61
Publisher Name: Springer, Berlin, Heidelberg
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