Abstract
The silicon-scaling revolution presents a multitude of challenges as technology progresses into the nanoscale era. One of these challenges are new data structures required for nanoscale designs which are inherently three-dimensional (3D). The majority of the currently developed 3D data structures are extensions of their well known 2D predecessors. New data structures specifically designed for the 3D nanoscale designs—which are truly able to fulfill the new demand determined by 3D integration technologies—are required. In this paper a systematic overview of main data structures that have been developed for 3D designs is presented. Their characteristics are investigated in detail in order to draw conclusions about the application potential in the new, nanoscale 3D context.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
Notes
- 1.
It is the same complexity class as 3D-subTCG but delivers a 15x speed up compared to 3D-subTCG when applied to the 3D-ami49 benchmark.
- 2.
The original O(\(n^3\)) complexity was making the 3D-BSG practically unusable.
- 3.
Measured in terms of effectiveness, i.e., volume ratio over simulated annealing time (faster and less white space). The comparison limited to a small number of boxes (100) and short search times (1000 s on a Pentium IV 3.2 GHz).
- 4.
Two arbitrary solutions can be connected by a set of operations. Higher reachability means a lower number of required operations.
References
Berntsson, J., Tang, M.: A slicing structure representation for the multi-layer floorplan layout problem. In: EvoWorkshops 2004, LNCS. vol. 3005, pp. 188–197. School of Computing Science and Software Engineering Queensland University of Technology QLD 4001, Australia. Springer, Heidelberg (2004)
Chan, H.H., Adya, S.N., Markov, I.L.: Are floorplan representations important in digital design? In: ISPD ’05: Proceedings of the 2005 International Symposium on Physical Design, pp. 129–136. ACM, New York (2005). doi:10.1145/1055137.1055164
Chang, Y.C., Chang, Y.W., Wu, G.M., Wu, S.W.: B*-Trees: A new representation for non-slicing floorplans. In: DAC ’00: Proceedings of the 37th Conference on Design Automation, pp. 458–463. ACM, New York (2000). doi:10.1145/337292.337541
Cheng, L., Deng, L., Wong, M.D.F.: Floorplanning for 3-D VLSI design. In: ASP-DAC ’05: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, pp. 405–411. ACM, New York (2005). doi:10.1145/1120725.1120899
Cong, J., Wei, J., Zhang, Y.: A thermal-driven floorplanning algorithm for 3D ICs. In: IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004. pp. 306–313 (2004)
Deng, Y., Maly, W.P.: Interconnect characteristics of 2.5-D system integration scheme. In: ISPD ’01: Proceedings of the 2001 International Symposium on Physical Design, pp. 171–175. ACM, New York (2001). doi:10.1145/369691.369763
Fischbach, R., Lienig, J., Meister, T.: From 3D circuit technologies and data structures to interconnect prediction. In: SLIP ’09: Proceedings of the 11th International Workshop on System Level Interconnect Prediction, pp. 77–84. ACM, New York (2009). doi:10.1145/1572471.1572485
Fujiyoshi, K., Kawai, H., Ishihara, K.: DTS: A tree based representation for 3D-block packing. In: Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS 2007, pp. 1045–1048 (2007). doi:10.1109/ISCAS.2007.378149
Fujiyoshi, K., Kawai, H., Ishihara, K.: A tree based novel representation for 3D-block packing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5), 759–764 (2009). doi:10.1109/TCAD.2009.2015424
Guo, P.N., Cheng, C.K., Yoshimura, T.: An O-Tree representation of non-slicing floorplan and its applications. In: DAC ’99: Proceedings of the 36th ACM/IEEE Conference on Design Automation, pp. 268–273. ACM, New York (1999). doi:10.1145/309847.309928
Hong, X., Huang, G., Cai, Y., Gu, J., Dong, S., Cheng, C.K., Gu, J.: Corner Block List: an effective and efficient topological representation of non-slicing floorplan. In: International Conference on Computer Aided Design (ICCAD), pp. 8–12 (2000). doi:10.1109/ICCAD.2000.896442
ITRS: International Technology Roadmap for Semiconductors. Technical Report. ESIA, JEITA, KSIA, TSIA and SIA (2009). http://www.itrs.net/reports.html
Kirkpatrick, S., Gelatt, C.D., Vecchi, M.P.: Optimization by simulated annealing. Science 220(4598), 671–680 (1983)
Kohira, Y., Kodama, C., Fujiyoshi, K., Takahashi, A.: 3D-Floorplanning for scheduling of dynamically reconfigurable systems. IEIC Tech. Report. 104(478), 37–42 (2004) (in Japanese)
Kohira, Y., Kodama, C., Fujiyoshi, K., Takahashi, A.: Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. In: Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS 2006, pp. 4487–4490 (2006). doi:10.1109/ISCAS.2006.1693626
Law, J.H.Y., Young, E.F.Y., Ching, R.L.S.: Block alignment in 3D floorplan using layered TCG. In: GLSVLSI ’06: Proceedings of the 16th ACM Great Lakes Symposium on VLSI, pp. 376–380. ACM, New York (2006). doi:10.1145/1127908.1127994
Ma, Y., Hong, X., Dong, S., Cheng, C.K.: 3D CBL: An efficient algorithm for general 3D packing problems. In: Proceedings of the 48th Midwest Symposium on Circuits and Systems. vol. 2, pp. 1079–1082 (2005). doi:10.1109/MWSCAS.2005.1594292
Ma, Y., Li, Z., Hong, X., Cong, J., Dong, S.: Cubic packing with various candidates for 3D IC design. In: Proceedings of the 8th International Conference on Solid-State and Integrated Circuit Technology ICSICT ’06, pp. 2079–2081 (2006). doi:10.1109/ICSICT.2006.306622
Murata, H., Fujiyoshi, K., Nakatake, S., Kajitani, Y.: Rectangle-packing-based module placement. In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD-95. Digest of Technical Papers, pp. 472–479 (1995). doi:10.1109/ICCAD.1995.480159
Nakatake, S., Fujiyoshi, K., Murata, H., Kajitani, Y.: Module placement on BSG-structure and IC layout applications. In: ICCAD ’96: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, pp. 484–491. IEEE Computer Society, Washington, DC (1996)
Ohta, H., Yamada, T., Kodama, C., Fujiyosi, K.: The O-Sequence: Representation of 3D-floorplan dissected by rectangular walls. In: Proceedings of the Ph.D Research in Microelectronics and Electronics 2006, pp. 317–320 (2006). doi:10.1109/RME.2006.1689960
Sakanushi, K., Kajitani, Y.: The Quarter-State Sequence (Q-Sequence) to represent the floorplan and applications to layout optimization. In: Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems IEEE APCCAS 2000, pp. 829–832 (2000). doi:10.1109/APCCAS.2000.913649
Sakanushi, K., Kajitani, Y., Mehta, D.P.: The Quarter-State Sequence floorplan representation. IEEE Trans. Circuits Syst. Regul. Pap. 50(3), 376–386 (2003). doi:10.1109/TCSI.2003.809442
Salewski, S., Olbrich, M., Barke, E.: LIFT: Ein multi-layer IC floorplanning tool. In: 11. E.I.S.-Workshop: Entwurf Integrierter Schaltungen und Systeme (2003)
Shiu, P.H., Ravichandran, R., Easwar, S., Lim, S.K.: Multi-layer floorplanning for reliable System-on-Package. In: Proceedings of the International Symposium on Circuits and Systems ISCAS ’04. vol. 5, pp. V-69-V-72 (2004)
Wang, R., Young, E.F.Y., Zhu, Y., Graham, F.C., Graham, R., Cheng, C.K.: 3-D floorplanning using Labeled Tree and Dual Sequences. In: ISPD ’08: Proceedings of the 2008 International Symposium on Physical Design, pp. 54–59. ACM, New York (2008). doi:10.1145/1353629.1353641
Yamagishi, H., Ninomiya, H., Asai, H.: Three dimensional module packing by simulated annealing. In: IEEE Congress on Evolutionary Computation. vol. 2, pp. 1069–1074 (2005). doi:10.1109/CEC.2005.1554809
Yamazaki, H., Sakanushi, K., Nakatake, S., Kajitani, Y.: The 3D-packing by meta data structure and packing heuristics. IEICE Trans. Fundam. Electron. Commun. Comput. E83-A(4), 639–645 (2000)
Yao, B., Chen, H., Cheng, C.K., Graham, R.: Revisiting floorplan representations. In: ISPD ’01: Proceedings of the International Symposium on Physical Design 2001, pp. 138–143. ACM, New York (2001). doi:10.1145/369691.369753
Yuh, P.H., Yang, C.L., Chang, Y.W.: Temporal floorplanning using the T-Tree formulation. In: Proceedings of the IEEE/ACM International Conference on Computer Aided Design ICCAD-2004, pp. 300–305 (2004). doi:10.1109/ICCAD.2004.1382590
Yuh, P.H., Yang, C.L., Chang, Y.W.: Placement of defect-tolerant digital microfluidic biochips using the T-Tree formulation. J. Emerg. Technol. Comput. Syst. 3(3), 13 (2007). doi:10.1145/1295231.1295234
Yuh, P.H., Yang, C.L., Chang, Y.W.: Temporal floorplanning using the three-dimensional transitive closure subgraph. ACM Trans. Des. Autom. Electron. Syst. 12(4), 37 (2007). doi:10.1145/1278349.1278350
Yuh, P.H., Yang, C.L., Chang, Y.W.: T-Trees: A tree-based representation for temporal and three-dimensional floorplanning. ACM Trans. Des. Autom. Electron. Syst. 14(4), 1–28 (2009). doi:10.1145/1562514.1562519
Yuh, P.H., Yang, C.L., Chang, Y.W., Chen, H.L.: Temporal floorplanning using 3D-subTCG. In: C.L. Yang (ed.) Proceedings of the Asia and South Pacific Design Automation Conference the ASP-DAC 2004, pp. 725–730 (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Fischbach, R. (2012). 3D Data Structures for Nanoscale Design. In: Gerlach, G., Wolter, KJ. (eds) Bio and Nano Packaging Techniques for Electron Devices. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28522-6_5
Download citation
DOI: https://doi.org/10.1007/978-3-642-28522-6_5
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-28521-9
Online ISBN: 978-3-642-28522-6
eBook Packages: Chemistry and Materials ScienceChemistry and Material Science (R0)