Abstract
In this work a novel approach to automatically generate hardware is introduced that allows accelerated simulation of artificial neural networks (ANN) on field-programming gate arrays (FPGAs). A compiler architecture has been designed that primarily aims at reducing the development effort for non-hardware developers. This is done by implementing automatic generation of accordingly adjusted hardware processors. Deduced from high-level OpenCL source code, the processors are able to spatially map ANNs in a massive parallel fashion.
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Hoffmann, J., Güttler, F., El-Laithy, K., Bogdan, M. (2012). Cyfield-RISP: Generating Dynamic Instruction Set Processors for Reconfigurable Hardware Using OpenCL. In: Villa, A.E.P., Duch, W., Érdi, P., Masulli, F., Palm, G. (eds) Artificial Neural Networks and Machine Learning – ICANN 2012. ICANN 2012. Lecture Notes in Computer Science, vol 7552. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33269-2_22
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DOI: https://doi.org/10.1007/978-3-642-33269-2_22
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