Abstract
Temporal logic has been extensively investigated for proving properties of programs-particularly for programs that involve nondeterminism or concurrency ([9], [11], [12]). However, most of the verification techniques developed so far involve manual construction of proofs, a task that may require a good deal of ingenuity and is usually quite tedious. In a series of papers ([1], [5], [6], [10]) we have argued that proof construction is unnecessary in the case of finite state systems and can be replaced by a model theoretic approach which will mechanically determine if the system meets a specification expressed in a propositional temporal logic. In this paper we survey that work and give a detailed example of how our approach might be used in verifying a finite state hardware controller.
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Clarke, E.M., Browne, M.C., Emerson, E.A., Sistla, A.P. (1985). Using Temporal Logic for Automatic Verification of Finite State Systems. In: Apt, K.R. (eds) Logics and Models of Concurrent Systems. NATO ASI Series, vol 13. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-82453-1_1
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DOI: https://doi.org/10.1007/978-3-642-82453-1_1
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