Abstract
Physical Unclonable Functions (PUFs) are specialized circuits with applications including key generation and challenge-response authentication. PUF properties such as low cost and resistance to invasive attacks make PUFs well-suited to embedded devices. Yet, given how infrequently the specialized capabilities of a PUF may be needed, the silicon area dedicated to it is largely idle. This inefficient resource usage is at odds with the cost minimization objective of embedded devices. Motivated by this inefficiency, we propose the Bitline PUF – a novel PUF that uses modified wordline drivers together with SRAM circuitry to enable challenge-response authentication. The number of challenges that can be applied to the Bitline PUF grows exponentially with the number of SRAM rows, and these challenges can be applied at any time without power cycling. This paper presents in detail the workings of the Bitline PUF, and shows that it achieves high throughput, low latency, and uniqueness across instances. Circuit simulations indicate that the Bitline PUF responses have a nominal bit-error-rate (BER) of 0.023 at 1.2 V supply and 27°C, and that BER does not exceed 0.076 when supply voltage is varied from 1.1 V to 1.3 V, or when temperature is varied from 0°C to 80°C. Because the Bitline PUF leverages existing SRAM circuitry, its area overhead is only a single flip-flop and two logic gates per row of SRAM. The combination of high performance and low cost makes the Bitline PUF a promising candidate for commercial adoption and future research.
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Anis, M., Aburahma, M.H.: Leakage Current Variability in Nanometer Technologies. In: 2005 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications, pp. 60–63 (2005)
ARM Limited. ARM Security Technology: Building a secure system using trustzone technology, http://infocenter.arm.com/help/topic/com.arm.doc.prd29-genc-009492c/PRD29-GENC-009492C_trustzone_security_whitepaper.pdf (last Viewed June 13, 2014)
Bhargava, M., Cakir, C., Mai, K.: Attack Resistant Sense Amplifier Based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses. In: 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST (2010)
Bhargava, M., Cakir, C., Mai, K.: Reliability Enhancement of bi-stable PUFs in 65nm Bulk CMOS. In: 2012 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 25–30 (2012)
Chen, Q., Csaba, G., Lugli, P., Schlichtmann, U., Rührmair, U.: The Bistable Ring PUF: A New Architecture for Strong Physical Unclonable Functions. In: 2011 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 134–141 (2011)
Gassend, B., Clarke, D., Van Dijk, M.: Silicon Physical Random Functions. In: Proceedings of the 9th ACM Conference on Computer and Communications Security, pp. 148–160 (2002)
Guajardo, J., Kumar, S.S., Schrijen, G.-J., Tuyls, P.: FPGA Intrinsic PUFs and Their use for IP Protection. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 63–80. Springer, Heidelberg (2007)
Heald, R., Wang, P.: Variability in Sub-100nm SRAM Designs. In: IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004, pp. 347–352 (2004)
Helfmeier, C., Boit, C., Nedospasov, D., Seifert, J.P.: Cloning Physically Unclonable Functions. In: 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 1–6 (2013)
Hofer, M., Boehm, C.: An Alternative to Error Correction for SRAM-like PUFs. In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 335–350. Springer, Heidelberg (2010)
Holcomb, D.E., Burleson, W.P., Fu, K.: Power-up SRAM State as an Identifying Fingerprint and Source of True Random Numbers. IEEE Transactions on Computers (2009)
Holcomb, D.E., Rahmati, A., Salajegheh, M., Burleson, W.P., Fu, K.: DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification. In: Hoepman, J.-H., Verbauwhede, I. (eds.) RFIDSec 2012. LNCS, vol. 7739, pp. 165–179. Springer, Heidelberg (2013)
Joachims, T.: Making Large-Scale SVM Learning Practical. In: Schölkopf, B., Burges, C., Smola, A. (eds.) Advances in Kernel Methods - Support Vector Learning, pp. 169–184. MIT Press, Cambridge (1999)
Kohno, T., Broido, A., Claffy, K.: Remote Physical Device Fingerprinting. In: 2005 IEEE Symposium on Security and Privacy, pp. 211–225 (2005)
Krishna, A.R., Narasimhan, S., Wang, X., Bhunia, S.: MECCA: A Robust Low-overhead PUF Using Embedded Memory Array. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 407–420. Springer, Heidelberg (2011)
Lee, J.W., Lim, D., Gassend, B., Suh, G.E., Van Dijk, M., Devadas, S.: A Technique to Build a Secret Key in Integrated Circuits for Identification and Authentication Applications. In: 2004 Symposium on VLSI Circuits, 2004. Digest of Technical Papers, pp. 176–179 (2004)
Lim, D.: Extracting Secret Keys from Integrated Circuits. MS thesis, Massachusetts Institute of Technology (May 2004)
Lin, L., Holcomb, D.E., Krishnappa, D.K., Shabadi, P., Burleson, W.P.: Low-power Sub-threshold Design of Secure Physical Unclonable Functions. In: ISLPED 2010: Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design (August 2010)
Lofstrom, K., Daasch, W.: IC Identification Circuit Using Device Mismatch. In: International Solid State Circuits Conference, pp. 372–373 (2000)
Majzoobi, M., Ghiaasi, G., Koushanfar, F., Nassif, S.R.: Ultra-low Power Current-based PUF. In: 2011 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2071–2074 (2011)
Majzoobi, M., Koushanfar, F., Potkonjak, M.: Lightweight Secure PUFs. In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2008, pp. 670–673 (2008)
Mathew, S.K., Satpathy, S.K., Anders, M.A., Kaul, H., Hsu, S.K., Agarwal, A., Chen, G.K., Parker, R.J., Krishnamurthy, R.K., De, V.: A 0.19pJ/b PVT-variation-Tolerant Hybrid Physically Unclonable Function Circuit for 100% Stable Secure Key Generation in 22nm CMOS. In: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 278–279 (2014)
Nii, K., Tsukamoto, Y., Yoshizawa, T., Imaoka, S., Yamagami, Y., Suzuki, T., Shibayama, A., Makino, H., Iwade, S.: A 90-nm Low-power 32-kB Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications. IEEE Journal of Solid-State Circuits 39(4), 684–693 (2004)
Okumura, S., Yoshimoto, S., Kawaguchi, H., Yoshimoto, M.: A 128-bit Chip Identification Generating Scheme Exploiting SRAM Bitcells with Failure Rate of 4.45*10− 19. In: Proceedings of the 37th European Solid-State Circuits Conference, pp. 527–530 (2011)
Oren, Y., Sadeghi, A.-R., Wachsmann, C.: On the Effectiveness of the Remanence Decay Side-channel to Clone Memory-based PUFs. In: Bertoni, G., Coron, J.-S. (eds.) CHES 2013. LNCS, vol. 8086, pp. 107–125. Springer, Heidelberg (2013)
Pappu, R., Recht, B., Taylor, J.: Physical One-Way Functions. Science (2002)
Pelgrom, M.J.M., Duinmaijer, A.C.J., Welbers, A.P.G.: Matching Properties of MOS Transistors. IEEE Journal of Solid-State Circuits 24(5), 1433–1439 (1989)
Prabhu, P., Akel, A., Grupp, L.M., Yu, W.-K.S., Suh, G.E., Kan, E., Swanson, S.: Extracting Device Fingerprints from Flash Memory by Exploiting Physical Variations. In: McCune, J.M., Balacheff, B., Perrig, A., Sadeghi, A.-R., Sasse, A., Beres, Y. (eds.) Trust 2011. LNCS, vol. 6740, pp. 188–201. Springer, Heidelberg (2011)
Predictive Technology Model. 90nm NMOS and PMOS BSIM4 Models, http://ptm.asu.edu/modelcard/2006/90nm_bulk.pm (last Viewed June 13, 2014)
Predictive Technology Model. Interconnect, http://ptm.asu.edu/interconnect.html (last Viewed June 13, 2014)
Qazi, M., Tikekar, M., Dolecek, L., Shah, D., Chandrakasan, A.: Loop Flattening & Spherical Sampling: Highly Efficient Model Reduction Techniques for SRAM Yield Analysis. In: DATE 2010: Proceedings of the Conference on Design, Automation and Test in Europe (March 2010)
Rührmair, U., Holcomb, D.E.: PUFs at a Glance. In: DATE 2014: Proceedings of the Conference on Design, Automation and Test in Europe (March 2014)
Rührmair, U., Sehnke, F., Sölter, J., Dror, G., Devadas, S., Schmidhuber, J.: Modeling Attacks on Physical Unclonable Functions. In: CCS 2010: Proceedings of the 17th ACM Conference on Computer and Communications Security (2010)
Seevinck, E., List, F.J., Lohstroh, J.: Static-noise Margin Analysis of MOS SRAM cells. IEEE Journal of Solid-State Circuits 22(5), 748–754 (1987)
Su, Y., Holleman, J., Otis, B.: A 1.6 pj/bit 96% Stable chip-ID Generating Circuit Using Process Variations. In: International Solid State Circuits Conference, pp. 406–407 (2007)
Suh, G.E., Devadas, S.: Physical Unclonable Functions for Device Authentication and Secret Key Generation. In: DAC 2007: Proceedings of the 44th Annual Design Automation Conference (2007)
Yao, Y., Kim, M., Li, J., Markov, I.L., Koushanfar, F.: ClockPUF: Physical Unclonable Functions Based on Clock Networks. In: DATE 2013: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 422–427 (2013)
Zheng, Y., Hashemian, M.S., Bhunia, S.: RESP: A Robust Physical Unclonable Function Retrofitted into Embedded SRAM Array. In: DAC 2013: Proceedings of the 50th Annual Design Automation Conference (2013)
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Holcomb, D.E., Fu, K. (2014). Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM. In: Batina, L., Robshaw, M. (eds) Cryptographic Hardware and Embedded Systems – CHES 2014. CHES 2014. Lecture Notes in Computer Science, vol 8731. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-44709-3_28
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DOI: https://doi.org/10.1007/978-3-662-44709-3_28
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