Abstract
In SoC design, isolation cells are used between different power domains to prevent the floating outputs/inputs of the power gated blocks from affecting the operations of the active circuits. At present, the low power SoCs use millions of isolation cells to implement different power gating modes and the isolation cells occupy considerable silicon area of the SoC. Also, the isolation values in low power designs are pre-determined (either fixed to ‘0’ or ‘1’ in design itself) and are non-configurable in real time operation. Hence, any incorrect isolation value may render the device useless in low power modes. In this paper, we propose a modified clamping circuit design to reduce the area and delay of the isolation cells. We also propose a method to configure the isolation values for certain qualifier signals and the subsequent entry process of the power gated modules into deep-sleep mode. The results show that the proposed technique can improve reliability of the power gating modes and reduce 30% to 50% of isolation cell area compared to that of the conventional isolation technique using logic gates.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Keating, M., Flynn, D., Aitkens, R., Gibbons, A., Shi, K.: Low-Power Methodology Manual for System-On-Chip Design. Springer, New York (2007). https://doi.org/10.1007/978-0-387-71819-4. www.lpmm-book.org
Severson, M.: Low Power SoC Design and Automation. University of California San Diego, Computer Science department, 27 July 2009. https://cseweb.ucsd.edu/classes/wi10/cse241a/slides/Matt.pdf
Ali, I., Sharma, P.: System for isolating integrated circuit power domains. US Patent US9407264B1 (2016)
Different SoC products description, documentation and reference manual of SoC design 1 (T1040), SoC design 2 (T1024), SoC design 3 (LS1020). www.nxp.com
AMBA, AXI3, AXI4 and ACE Bus Specification. https://www.arm.com/products/system-ip/amba-specifications.php
IEEE standard 1801-2009 (UPF). www.ieee.org
Carver, S., Mathur, A., Sharma, L., Subbarao, P., Urish, S., Wang, Q.: Low-power design using the Si2 common power format. IEEE Des. Test Comput. 29(2), 62–70 (2012)
Ghosh, P., Ghosh, S.: Method to reduce power and wake-up time in low power modes. In: Proceedings of IEEE International Conference Conecct, January 2013, IISc, Bangalore, India (2013)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Ghosh, P., Ghosh, J. (2017). A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_59
Download citation
DOI: https://doi.org/10.1007/978-981-10-7470-7_59
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-7469-1
Online ISBN: 978-981-10-7470-7
eBook Packages: Computer ScienceComputer Science (R0)