Abstract
Quantum-dot cellular automata (QCA) is a likely candidate for future low power nano-scale electronic devices. Recently, configurable QCA designs are studied due to its low device cost, low power consumption and efficient utilization of device area. In this direction, a design of level triggered configurable flip-flop (LTCFF) is proposed which can be configured to D, T and JK flip-flop. A realistic version of the proposed LTCFF is also implemented using a universal, scalable and efficient (USE) clocking scheme. The performance of the proposed LTCFF is evaluated in terms of area occupied, no. of cells and delay which shows significant improvement over existing designs. The design flexibility of LTCFF is further tested realizing n-bit Counter/Shift Register. Moreover, the single stuck-at faults of the proposed LTCFF are tested with the help of its control inputs. All the proposed designs are verified using QCADesigner simulator.
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This entire research has been carried out under the Visvesvaraya PhD scheme which is managed by the Media Lab Asia, India and is under the supervision of the Electronics and IT Department, Ministry of Communications and IT, Government of India.
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Goswami, M., Choudhury, M.R., Sen, B. (2019). A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_38
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