Abstract
As digital signal processing systems become larger and clock rates increase, the typical design approach using global clock synchronization will become increasingly difficult. The application of asynchronous clock-free designs to high-performance digital signal processing systems is one promising approach to alleviating this problem. To demonstrate this approach for a typical signal processing task, the system architecture and circuit design of a chip set for implementing high-rate adaptive lattice filters using the asynchronous design techniques is presented.
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This research was sponsored in part by the Semiconductor Research Corporation and by DARPA.
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Meng, T.H.Y., Brodersen, R.W. & Messerschmitt, D.G. A clock-free chip set for high-sampling rate adaptive filters. J VLSI Sign Process Syst Sign Image Video Technol 1, 345–365 (1990). https://doi.org/10.1007/BF00929927
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DOI: https://doi.org/10.1007/BF00929927