Abstract
A novel reconfiguration algorithm for 2-D processor arrays is proposed to achieve a high survival rate through the efficient utilization of the given interconnection resources. The main idea is to parition the array into as small units, called subranges, as possible, while preserving the characteristics of array reconfigurability. The proposed strategy employs a flexible index mapping strategy, thereby achieving cell assignments which maximize the utilization of the given interconnection resources. However, some cell assignments may not result in the successful reconfiguration due to the lack of interconnection resources. A method of associating the connectivity requirement of a reconfiguration algorithm with given interconnection resources is developed to check possible resource conflicts. The rationale behind our approach is that the probability of cell assignments causing such resource conflicts is pretty low. Furthermore, most resource conflicts can be resolved by the proposed resolution techniques. Simulation results show that our approach achieves a higher survival rate than the previous designs.
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References
I. Koren and D.K. Pradhan, “Modeling the effect of redundancy or yield and performance of VLSI systems”,IEEE Trans. on Computers, 1987, pp. 344–355.
J.H. Kim and S.M. Reddy, “On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement,”IEEE Trans. on Computers, 1989, pp. 515–525.
S.Y. Kuo and W.K. Fuchs, “Efficient spare allocation in reconfiguration arrays”,IEEE Design and Test, 1987, pp. 24–31.
M. Chean and J.A.B. Fortes, “The full-of-suitable-spares (FUSS) approach to hardware reconfiguration for fault-tolerant processor arrays”,IEEE Trans. on Computers, 1990, pp. 564–571.
T. Leighton and C.E. Leiserson, “Wafer scale integration of systolic arrays”,IEEE Trans. on Computers, 1985, pp. 448–461.
F. Lombardi, R. Negrini, and R. Stefanelli, “Reconfiguration of VLSI arrays by covering,”IEEE Trans. on Computer Aided Design, 1989, pp. 952–965.
R. Negrini, R. Stefanelli, and M.G. Sami, “Fault tolerance technique for array structures used in supercomputing”,IEEE Computer, 1986, pp. 78–87.
P.K. Rhee, J.H. Kim, and H.Y. Youn, “A novel reconfiguration scheme for 2-D processor arrays,”ICCAD-89, 1989, pp. 230–233.
P.K. Rhee and J.H. Kim, “Channel complex analysis for reconfigurable VLSI/WSI processor arrays,”Intl. Conf. on Application-Specific Array Processors, 1990.
V.P. Roychowdhury, J. Bruck, and T. Kailath, “Efficient algorithm for reconfiguration in VLSI/WSI arrays,”IEEE Trans. on Computers, 1990, pp. 480–489.
S.-Y. Kung, S.-N. Jean, C.-W. Chang, “Fault-tolerant array processors using single-track switches,”IEEE Trans. on Computers, 1989, pp. 501–514.
P.K. Rhee, “On the reconfiguration of VLSI/WSI array processors,” Ph.D. Thesis, University of SW Louisiana, 1990.
M. Sami and R. Stefanelli, “Fault-tolerant computing approaches,” inSystolic Signal Processing Systems, New York: Marcel Dekker, Inc., E. Swartzlander, ed., 1987.
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Kim, J.H., Rhee, P.K. A resource-efficient reconfiguration algorithm of VLSI 2-D processor arrays. J VLSI Sign Process Syst Sign Image Video Technol 4, 317–330 (1992). https://doi.org/10.1007/BF00930643
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DOI: https://doi.org/10.1007/BF00930643