Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content
Springer Nature Link
Log in

Verifying the summit bus converter protocols with symbolic model checking

  • Published:
Formal Methods in System Design Aims and scope Submit manuscript

Abstract

We report on our investigation of a new verification tool, the Symbolic Model Verifier (SMV), created at Carnegie Mellon University. We have successfully, employed this tool to detect deadlock in an industrial design, namely, Hewlett-Packard's Summit bus converter chips. In addition to locating a known deadlock in the original chip design and checking its solution, we successfully detected other previously unknown defects in the design. In our experiments, we were able to verify properties on finite-state models of the circuit with 150 to 200 state variables in a matter of minutes.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. M.C. Browne, E.M. Clarke, D.L. Dill, and B. Mishra, Automatic verification of sequential circuits using temporal logic.IEEE Transactions on Computers C35(12): 1035–1044, December 1986.

    Google Scholar 

  2. J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Sequential circuit verification using symbolic model checking. In27th ACM/IEEE Design Automation Conference, IEEE Computer Society Press, Los Alamitos, CA, pp. 46–51, June 1990.

    Google Scholar 

  3. J.R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill, and L.J. Hwang. Symbolic model checking: 1020 states and beyond. InFifth Annual IEEE Symposium on Logic in Computer Science, IEEE Computer Society Press, Los Alamitos CA, June 1990, pp. 428–439.

    Google Scholar 

  4. E.M. Clarke, E.A. Emerson, and A.P. Sistla. Automatic verification of finite-state concurrent systems using temporal logic.ACM Transactions on Programming Languages and Systems, 8(2): 244–263, April 1986.

    Google Scholar 

  5. Acme Bus Converter External Reference Specification. Hewlett-Packard, Mainline Systems Lab, Cupertino, CA, May 1991, internal document.

  6. SUMMIT Bus Converter External Reference Specification. Hewlett-Packard, Mainline Systems Lab, Cupertino, CA, August 1990, internal document.

  7. K.L. McMillan and J. Schwalbe. Formal verification of the Encore Gigamax cache consistency protocol. InInternational Symposium on Shared Memory Multiprocessors, pp. 242–251, 1991.

  8. R.E. Bryant, Graph-based algorithms for boolean function manipulation.IEEE Transactions on Computers, C35(8): 677–691, August 1986.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Hewlett-Packard Company, 94303, Palo Alto, CA

    Cheryl Harkness

  2. Department of Computer Science, Stanford University, 94305, Stanford, CA

    Elizabeth Wolf

Authors
  1. Cheryl Harkness
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Elizabeth Wolf
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Harkness, C., Wolf, E. Verifying the summit bus converter protocols with symbolic model checking. Form Method Syst Des 4, 83–97 (1994). https://doi.org/10.1007/BF01384079

Download citation

  • Received:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01384079

Keywords

Search

Navigation