Abstract
The number of document compression algorithms is increasing due to the expanded information exchange in our society and due to the increasing quality demands for color documents. For these purposes, high quality and complex compression algorithms are needed, in order to keep the memory size and channel capacity within realistic bounds. In addition, these algorithms must be executed within a certain real-time specification, in order to reduce the user wait times. In this article, an optimized RBN-algorithm for coding true color documents will be used as a test vehicle. Unfortunately, the typical properties of such high-throughput algorithms restricts the possible real-time realizations. We believe that an application-specific design approach supported with powerful CAD-tools is the most efficient implementation for these type of applications when a reasonable time-to-market needs to be achieved. An efficient dedicated architecture is proposed, based on a lowly multiplexed co-operating data-path style. As for most complex video applications, the cost minimization and performance optimization are highly dependent on the memory organization. Hence the latter is the most important topic of this article. The architectural design process has been traversed mostly manually with use of some prototype synthesis tools from the merging CATHEDRAL-3 synthesis environment.
Similar content being viewed by others
References
H. Spriggs and C. Nightingale, “Recursive binary nesting: A quadtree approach to image compression,” Proceedings PCS, 1986.
K. Vanhoof, S. Desmet, R. Rommelaere and A. Oosterlinck, “Comparison of two interpolative coding methods: DIDT and RBN,”Proc. SPIE, vol. 829, 1987, pp. 109–114.
T. Gijbels, L. Van Eycken, A. Oosterlinck, S. Note and F. Catthoor, “An ASIC-architecture for VLSI-implementation of the RBN-algorithm,”IEEE International Conference and Pattern Recognition, 1990.
A.N. Netravali and B.G. Haskell,Digital Pictures, Plenum Publishing Corporation, 1988.
M. Sugai, A. Kanuma, K. Suzuki and M. Kubo, “VLSI processor for image processing,”Proc. IEEE, 1987, pp. 1160–1165.
M. Yamashina, Y. Enomoto, T. Kunio, I. Tamitani, H. Harasaki, Y. Endo, T. Nishitani, M. Sato and K. Kikuchi, “A micropro-grammable real-time video signal processor (VSP) for motion compensation,”IEEE Journal of Solid-State Circuits, 1988, pp. 907–914.
T. Murakami, K. Kamizawa, M. Kameyama and S. Nakagawa, “A DSP architecture for 64 kbps motion video codec,”ISCAS, 1988, pp. 227–230.
F. Catthoor and H. De Man, “Application-specific architectural methodologies for high throughput digital signal and image processing,”Transactions on Acoustics, Speech, and Signal Processing, vol. 37, 1990, pp. 176–192.
S. Note, W. Geurts, F. Catthoor and H. DeMan, “CATHEDRAL-III: architecture-driven high-level synthesis for high throughput DSP applications,”Proc. 1991 Design Automation Conference, 1991.
P.N. Hilfinger, J. Rabaey, D. Genin, C. Scheers and H. De Man, “DSP specification using the silage language,”Proc. Int. Conf. on Acoustics, Speech and Signal Processing, 1990.
M.F.X.B. Van Swaaij, F.H.M. Franssen, F.V.M. Catthoor and H.J. De Man, “Modelling data flow and control flow for high level memory management,”EDAC92, 1992.
S. Note, F. Catthoor and H. De Man, “Definition and assignment of complex data-paths for high throughput applications,”IEEE International Conference on Computer-Aided Design, 1989.
D. Lanneer, F. Catthoor, G. Goossens, M. Pauwels and H. De Man, “Open-ended system for high-level synthesis of flexible signal processors,”Proceedings EDAC90, 1990, pp. 272–276.
W. Geurts, S. Note, F. Catthoor and H. De Man, “Partitioning-based allocation of dedicated data-paths in the architectural synthesis for high-throughput applications,”Proc. VLSI91 Conference, 1991.
D. Lanneer, S. Note, F. Depuydt, M. Pauwels, F. Catthoor, G. Goossens and H. De Man, “Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment,” in R. Camposano and W. Wolf,eds., Trends in High-Level Synthesis, Kluwer, 1991.
S.Y. Kung,VLSI Array Processors, Englewood Cliffs, N.J.: Prentice Hall, 1988.
I. Verbauwhede, F. Catthoor, J. Vandewalle and H. De Man, “Background memory synthesis for algebraic algorithms on multiprocessor DSP chips,”VLSI90, Elsevier, 1990, p. 209.
P.E.R. Lippens, J.L. Van Meerbergen, A. Van Der Werf, W.F.J. Verhaegh and B.T. McSweeney, “Memory synthesis for high speed DSP applications,”CICC, 1991, p. 11.7.1.
M.F.X.B. Van Swaaij, F.H.M. Franssen, F.V.M. Catthoor and H.J. De Man, “Modeling data flow and control flow for DSP system synthesis,”Journal of VLSI Signal Processing, Special issue on VLSI/DSP Design Methodologies, M. Bayoumi, ed., Kluwer, 1992.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Gijbels, T., Catthoor, F., van Eycken, L. et al. An application-specific architecture for the RBN-coder with efficient memory organization. J VLSI Sign Process Syst Sign Image Video Technol 5, 221–235 (1993). https://doi.org/10.1007/BF01581297
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF01581297