Abstract
The problems of self-timed behavior specification and verification are considered on the basis of an event model—Change Diagram (CD). The descriptive power of a CD model is demonstrated by comparing the CD with Signal Transition Graphs (STG). CD differs from STG by two types of causal relations (AND and OR) between events (in STG only AND-relation is presented). CD verification is shown to be reducible to an analysis of precedence and concurrency properties for events. These properties are hard to analyze directly by a cyclic CD. We suggest that the cyclic description be replaced by an equivalent acyclic one (called an unfolding) in order to solve the analysis problem. The notion of CD correctness is introduced, and the necessity and sufficiency of this notion for the implementation to be in self-timed class are shown. The polynomial algorithms for CD correctness verification are considered.
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References
D.E. Muller, Lecture notes on asynchronous circuits theory, Urbana: Univ. of Illinois, 1961.
J.L. Peterson,Petri Net Theory and the Modelling of Systems, New York: Prentice-Hall, Inc., 1981.
T.A. Chu, “Synthesis of self-timed VLSI circuits from graphtheoretic specification,”Proceedings of ICCD'87: IEEE Int. Conf. Comput. Design, 1987, pp. 220–223.
A. Mazurkiewicz, “Basic notion of trace theory,”LNCS, vol. 354, 1989, pp. 285–363.
G. Winskel, “An introduction to event structures,”LNCS, vol. 354, 1989, pp. 364–397.
A.J. Martin, “Programming in VLSI: From communicating processes to delay-insensitive circuits,” in C.A.R. Hoare ed.,UT Year of Programming Institute on Concurrent Programming, Reading, MA: Addison-Wesley, 1989.
S.M. Nowick and D.L. Dill, “Practicality of state-machine verification of speed-independent circuits,”Proceedings of IEEE ICCAD'89, 1989, pp. 266–269.
T.H. Meng, R.W. Brodersen and D.G. Messerschmitt, “Automatic synthesis of asynchronous circuits from high-level specification,”IEEE Transactions on CAD, vol. 8, 1989, pp. 1185–1205.
J.A. Brzozowski and J.C. Ebergen, “Recent developments in the design of asynchronous circuits,”LNCS, vol. 380, 1989, pp. 78–94.
V.I. Varshavsky, M.A. Kishinevsky, V.B. Marakhovsky, V.A. Peschansky, L.Ya. Rosenblum, A.R. Taubin and Tzirlin B.S.,Self-timed Control of Concurrent Processes, Boston, MA: Kluwer Academic Publishers, 1990.
V.I. Varshavsky, M.A. Kishinevsky, A.Yu. Kondratyev, L.Ya. Rosenblum and A.R. Taubin, “Models for specification and analysis of processes in asynchronous circuits,”Soviet Journal of Computer and Systems Sciences, vol. 26, 1989, pp. 61–76.
M.A. Kishinevsky, A.Yu. Kondratyev and A.R. Taubin, “Formal methods for self-timed design,”Proceedings of the Europ. Conf. on Design Automation (EDAC'91), 1991, pp. 197–201.
M.A. Kishinevsky, A.Yu. Kondratyev, A.R. Taubin and V.I. Varshavsky, “Analysis and identification of self-timed circuits,”Proceedings of IFIP 2nd Workshop on Designing Correct Circuits, Lyngby, Denmark, 1992, pp. 275–287.
V.I. Varshavsky, et al., “The self-timing in VLSI and VLSI-systems,” Avanproject Research Report, R&D Coop “Trassa,” PPI “Science Centre,” Leningrad, Moscow, 1991.
A.V. Aho, J.E. Hopcroft and J.D. Ullman,The Design and Analysis of Computer Algorithms, Reading, MA: Addison-Wesley, 1974.
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Kishinevsky, M.A., Kondratyev, A.Y. & Taubin, A.R. Specification and analysis of self-timed circuits. Journal of VLSI Signal Processing 7, 117–135 (1994). https://doi.org/10.1007/BF02108193
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DOI: https://doi.org/10.1007/BF02108193