Abstract
This paper presents design details for a bit-level systolic cell that has been recently introduced for imple menting digital signal processing (DSP) operations over finite rings.
This paper concentrates on the efficient construction of the basic cell, using a 3µ p-well CMOS technology. The design uses a 5-bit, 32-word dynamic ROM as the main computational element, and details of all elements of the cell are discussed with regard to minimizing the (Area. Period) product. The final cell design and simulation details are compared with a pipelined gated full-adder, designed in the same technology, which represents the most common type of binary bit-level systolic cell.
It is shown that the (Area. Period) product of the binary cell is 68% greater than that of the finite ring cell, but the power of the finite ring cell, in implementing fixed coefficient inner product multiplications, is much greater than that of the binary cell. There are also advantages associated with the reduction of the connectivity across the dynamic range, including clock-skew reduction, ease of testing, and fault detection. The conclusion is that in certain classes of DSP operations, this new cell can offer more than an order of magnitude improvement in (Area.Period) product of complete bit-level systolic arrays, over its binary counterpart.
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Jullien, G.A., Bird, P.D., Carr, J.T. et al. An efficient bit-level systolic cell design for finite ring digital signal processing applications. J VLSI Sign Process Syst Sign Image Video Technol 1, 189–207 (1989). https://doi.org/10.1007/BF02427794
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DOI: https://doi.org/10.1007/BF02427794