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Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s

Above Gbit/s data transmission using full-parallel block turbo decoder architecture

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Résumé

Cet article présente une nouvelle architecture atteignant de très haut débit pour le turbodécodage de codes produits. Ce type d’architecture est capable de décoder des codes produits reposant sur des codes binaires de type BCH ou des codes m-aire de type Reed Solomon. Son principal atout est qu’elle permet l’élimination des plans mémoires associés aux matrices générées par un code produit entre les différentes demi-itérations pour le turbodécodage. En fait, la solution architecturale que nous détaillons dans ce papier offre de nouvelles opportunités pour l’application des turbocodes dans des systèmes nécessitant des débits supérieurs au Gbit/s comme les systèmes de transmission sur fibre optique

Abstract

This paper presents a new circuit architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our full-parallel architecture is that it enables the memory block between each half-iteration to be removed. In fact, the proposed architecture opens the way to numerous applications such as optical transmission. In particular, our block turbo decoding architecture can support optical transmission at data rates above Gbit/s

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Correspondence to Christophe Jego.

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Jego, C., Adde, P. & Leroux, C. Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s. Ann. Telecommun. 62, 214–239 (2007). https://doi.org/10.1007/BF03253257

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  • DOI: https://doi.org/10.1007/BF03253257

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