Formal verification of digital circuits using symbolic ternary system models

Abstract

Ternary system modeling involves extending the traditional set of binary values {0, 1} with a third value X indicating an unknown or indeterminate condition. By making this extension, we can model a wider range of circuit phenomena. We can also efficiently verify sequential circuits in which the effect of a given operation depends on only a subset of the total system state.

This paper presents a formal methodology for verifying synchronous digital circuits using a ternary system model. The desired behavior of the circuit is expressed as assertions in a notation using a combination of Boolean expressions and temporal logic operators. An assertion is verified by translating it into a sequence of patterns and checks for a ternary symbolic simulator. The methodology has been used to verify a number of full scale designs.

This research was supported by the Defense Advanced Research Projects Agency, ARPA Order Number 4976, and by the National Science Foundation, under grant number MIP-8913667.

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