Abstract
Multi-threaded shared memory machines, like the commercial Tera MTA or the experimental SB-PRAM, have an extremely good performance on the Integer Sort benchmark of the NAS Parallel Benchmark Suite and are expected to scale. The number of CPU cycles is an order of magnitude lower than the numbers reported of general purpose distributed memory or shared memory machines; even vector computers are slower. The reasons for this behavior are investigated. It turns out that both machines can take advantage of a fetch-and-add operation and that due to multi-threading no time is lost waiting for memory accesses to complete. Except for non-scalable vector computers, the Cray T3E, which supports fetch-and-add but not multi-threading, is the only parallel computer that could challenge these machines.
This work was partly supported by the German Science Foundation (DFG) under contract SFB 124, TP D4.
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References
F. Abolhassan, R. Drefenstedt, J. Keller, W. J. Paul, and D. Scheerer. On the Physical Design of PRAMs. Computer Journal, 36(8):756–762, December 1993.
R. Alverson, P. Briggs, S. Coatney, S. Kahan, and R. Korry. Tera Hardware-Software Cooperation. In Proc. of Supercomputing ’97. San Jose, CA, November 1997.
R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, and B. Smith. The TERA Computer System. In Proc. of Intl. Conf. on Supercomputing, June 1990.
P. Bach, M. Braun, A. Formella, J. Friedrich, T. Grün, and C. Lichtenau. Building the 4 Processor SB-PRAM Prototype. In Proc. of the 30th Hawaii International Conference on System Sciences, pages 14–23, January 1997.
J. Boisseau, L. Carter, K.S. Gatlin, A. Majumdar, and S. Snavely. NAS Benchmarks on the Tera MTA. In Proc. of Workshop on Multi-Threaded Execution, Architecture and Compilation (M-TEAC 98), Las Vegas, February 1998.
M. Booth. US Patent 5247696. see http://www.patents.ibm.com, September 1993.
C. Engelmann and J. Keller. Simulation-based comparison of hash functions for emulated shared memory. In Proc. PARLE (Parallel Architectures and Languages Europe), pages 1–11, 1993.
D. Bailey et al. The NAS Parallel Benchmarks. RNR Technical Report RNR-94-007, NASA Ames Research Center, March 1994. see also http://science.nas.nasa.gov/Software/NPB.
A. Formella, T. Grün, and C.W. Kessler. The SB-PRAM: Concept, Design and Construction. In Draft Proceedings of 3rd International Working Conference on Massively Parallel Programming Models (MPPM-97), November 1997. see also http://www-wjp.cs.uni-sb.de/~formella/mppm.ps.gz.
A. Formella, J. Keller, and T. Walle. HPP: A High-Performance-PRAM. In Proceedings of the 2nd Europar, volume II of LNCS 1124, pages 425–434. Springer, August 1996.
T. Grün and M. A. Hillebrand. NAS Integersort on the SB-PRAM. Manuscript, available via http://www-wjp/~tgr/NASIS, May 1998.
T. Grün, T. Rauber, and J. Röhrig. Support for Efficient Programming on the SB-PRAM. International Journal of Parallel Programming, 26(3):209–240, June 1998.
D.E. Lenoski and W.-D. Weber. Scalable Shared-Memory Multiprocessing. Morgan Kaufmann Publishers, 1995.
NAS Parallel Benchmarks Home Page. http://science.nas.nasa.gov/Software/NPB/.
SB-PRAM Home Page. http://www-wjp.cs.uni-sb.de/sbpram.
S. L. Scott. Synchronization and Communication in the T3E Multiprocessor. In Proc. of the VII ASPLOS (Architectural Support for Programming Languages and Operating Systems) Conference, pages 26–36. ACM, October 1996.
Tera Computer Corporation Home Page. http://www.tera.com/.
J. van Leeuwen, editor. Handbook of Theoretical Computer Science, volume A, pages 869–941. Elsevier, 1990.
T. Walle. Das Netzwerk der SB-PRAM. PhD thesis, University of the Saarland, 1997. in German.
M. Zagha and G.E. Belloch. Radix Sort for Vector Multiprocessors. In Proc. of Supercomputing ’91, pages 712–721, New York, NY, November 1991.
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Grün, T., Hillebrand, M.A. (1998). NAS Integer sort on multi-threaded shared memory machines. In: Pritchard, D., Reeve, J. (eds) Euro-Par’98 Parallel Processing. Euro-Par 1998. Lecture Notes in Computer Science, vol 1470. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0057960
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