The first paper in this issue is authored by Tayade and Abraham of the University of Texas at Austin. The idea they put forward is that the delay of a path depends upon the dynamic coupling of it’s interconnects with those of other paths. The authors provide a mathematical formulation and a solution for the critical path testing. These critical paths are often different from those found by the conventional static analysis.

The second paper, authored by Mozaffari-Kermani and Reyhani-Masoleh of the University of Western Ontario in Canada, discusses a testable design for encryption hardware. The authors use a parity-based fault detection scheme.

The third paper describes a design for an output circuit that compacts the scan test response in the presence of don’t cares. This compactor uses a clock that is faster than the test clock. The paper is authored by Hilscher, Richter and Gössel of the University of Potsdam, Braun of Verigy Germany GmbH and Leininger of Infineon Technologies AG, Germany.

In the fourth paper, Holst and Wunderlich of University of Stuttgart, Germany, discuss a method of fault diagnosis. They use an effect-cause analysis to identify a suspected region of the circuit. Their procedure is independent of any fault model and does not require a fault dictionary.

The fifth paper is authored by Natale, Doulcier, Flottes and Rouzeyre of the University of Montpellier in France. The authors implement a fault tolerant design for encryption hardware. Redundancy is used but the overhead is kept low.

The final contribution in this issue is a JETTA Letter by Fernáandez of the Polytechnic University of Catalunya in Spain. The author discusses a method to assess the aging effects in semiconductor devices.

Readers must have noticed that this and the previous issues are double issues although they do not contain too many articles. The recent downturn in the semiconductor industry has caused a slowdown of our pipeline of papers. As the industry recovers we expect to get back to the usual six issues per year.