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Efficient multi-level fault simulation of HW/SW systems for structural faults

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Abstract

In recent technology nodes, reliability is increasingly considered a part of the standard design flow to be taken into account at all levels of embedded systems design. While traditional fault simulation techniques based on low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to properly cope with the complexity of modern embedded systems. Moreover, they do not allow for early exploration of design alternatives when a detailed model of the whole system is not yet available, which is highly required to increase the efficiency and quality of the design flow. Multi-level models that combine the simulation efficiency of high abstraction models with the accuracy of low-level models are therefore essential to efficiently evaluate the impact of physical defects on the system. This paper proposes a methodology to efficiently implement concurrent multi-level fault simulation across gate- and transaction-level models in an integrated simulation environment. It leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This combination of different models allows to accurately evaluate the impact of faults on the entire hardware/software system while keeping the computational effort low. Moreover, since only selected portions of the system require low-level models, early exploration of different design alternatives is efficiently supported. Experimental results obtained from three case studies are presented to demonstrate the high accuracy of the proposed method when compared with a standard gate/RT mixed-level approach and the strong improvement of simulation time which is reduced by four orders of magnitude in average.

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References

  1. Roy K, Mak T, Cheng K. Test consideration for nanometer-scale CMOS circuits. IEEE Des Test Comput, 2006, 23: 128–136

    Article  Google Scholar 

  2. Borkar S. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro, 2005, 25: 10–16

    Article  Google Scholar 

  3. Wattanapongsakorn N, Levitan S P. Reliability optimization models for embedded systems with multiple applications. IEEE Trans Reliab, 2004, 53: 406–416

    Article  Google Scholar 

  4. Cano J, Rios D. Reliability forecasting in complex hardware/software systems. In: Proceedings of the First International Conference on Availability, Reliability and Security, Vienna, Austria, 2006. 300–304

  5. Leveugle R, Cimonnet D, Ammari A. System-level dependability analysis with RT-level fault injection accuracy. In: Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, Cannes, France, 2004. 451–458

  6. Leveugle R, Hadjiat K. Multi-level fault injections in VHDL descriptions: Alternative approaches and experiments. J Electron Test, 2003, 19: 559–575

    Article  Google Scholar 

  7. Jhumka A, Klaus S, Huss S A. A dependability-driven system-level design approach for embedded systems. In: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 2005. 372–377

  8. Rothbart K, Neffe U, Steger C, et al. High level fault injection for attack simulation in smart cards. In: Proceedings of the 13th Asian Test Symposium, Kenting, Taiwan, China, 2004. 118–121

  9. Meyer W, Camposano R. Active timing multilevel fault-simulation with switch-level accuracy. IEEE Trans CAD Integr Circ Syst, 1995, 14: 1241–1256

    Article  Google Scholar 

  10. Santos M B, Teixeira J P. Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL. In: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 1999. 549

  11. Navabi Z, Mirkhani S, Lavasani M, et al. Using RT level component descriptions for single stuck-at hierarchical fault simulation. J Electron Test, 2004, 20: 575–589

    Article  Google Scholar 

  12. Gai S, Montessoro P L, Somenzi F. MOZART: a concurrent multilevel simulator. IEEE Trans CAD Integr Circ Syst, 1988, 7: 1005–1016

    Article  Google Scholar 

  13. Lentz K P, Homer J B. Handling behavioral components in multi-level concurrent fault simulation. In: Proceedings of the 33th Annual Simulation Symposium, Washington DC, USA, 2000. 149–156

  14. Hsiao M S, Patel J H. A new architectural-level fault simulation using propagation prediction of grouped fault-effects. In: Proceedings of International Conference on Computer Design, Austin, TX, USA, 1995. 628

  15. Sinanoglu O, Orailoglu A. RT-level fault simulation based on symbolic propagation. In: Proceedings of the 19th IEEE VLSI Test Symposium, Marina Del Rey, CA, USA, 2001. 240–245

  16. Misera S, Vierhaus H T, Sieber A. Simulated fault injections and their acceleration in SystemC. Microproc Microsyst Embed Hardware Des, 2008, 32: 270–278

    Article  Google Scholar 

  17. Beltrame G, Bolchini C, Miele A. Multi-level fault modeling for transaction-level specifications. In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI, Boston Area, MA, USA, 2009. 87–92

  18. Ghenassia F, ed. Transaction-Level Modeling with SystemC-TLM Concepts and Applications for Embedded Systems. NewYork: Springer, 2005

    Google Scholar 

  19. Gerstlauer A, Haubelt C, Pimentel A, et al. Electronic system-level synthesis methodologies. IEEE Trans CAD Integr Circ Syst, 2009, 28: 1517–1530

    Article  Google Scholar 

  20. Radetzki M. Object-oriented transaction level modelling. In: Huss S, ed. Advances in Design and Specification Languages for Embedded Systems. New York: Springer, 2007

    Google Scholar 

  21. Hwang Y, Abdi S, Gajski D. Cycle-approximate retargetable performance estimation at the transaction level. In: Proceedings of Design, Automation and Test in Europe, Munich, Germany, 2008. 3–8

  22. Cheema M, Hammami O. Introducing energy and area estimation in HW/SW design flow based on transaction level modeling. In: Proceedings of International Conference on Microelectronics, Dhahran, Saudi Arabia, 2006. 182–185

  23. Open SystemC Initiative (OSCI) TLM Working Group. Transaction level modeling standard 2 (OSCI TLM 2), June 2008. www.systemc.org

  24. Cai L, Gajski D. Transaction level modeling: an overview. In: Proceedings of International Conference on Hardware/Software Codesign and System Synthesis, Newport Beach, CA, USA, 2003. 19–24

  25. Mukherjee S S, Emer J S, Reinhardt S K. The soft error problem: An architectural perspective. In: Proceedings of the 11th International Conference on High-Performance Computer Architecture, San Francisco, CA, USA, 2005. 243–247

  26. Hiller M, Jhumka A, Suri N. EPIC: Profiling the propagation and effect of data errors in software. IEEE Trans Comput, 2004, 53: 512–530

    Article  Google Scholar 

  27. Radetzki M, Khaligh R S. Accuracy-adaptive simulation of transaction level models. In: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany, 2008. 788–791

  28. Kochte M A, Schaal M, Wunderlich H J, et al. Efficient fault simulation on many-core processors. In: Proceedings of ACM/IEEE Design Automation Conference, Anaheim, CA, USA, 2010

  29. Ulrich E, Baker T. The concurrent simulation of nearly identical digital networks. In: Proceedings of the 10th Workshop on Design Automation, New Delhi, India, 1973. 145–150

  30. Lee H K, Ha D S. Hope: An efficient parallel fault simulator for synchronous sequential circuits. In: Proceedings of ACM/IEEE Design Automation Conference, Anaheim, CA, USA, 1992. 336–340

  31. Lala P. Self-checking and Fault-tolerant Digital Design. San Fransisco: Morgan Kaufmann, 2001

    Google Scholar 

  32. da Silva Farina A, Prieto S. On the use of dynamic binary instrumentation to perform faults injection in transaction level models. In: Proceedings of the 4th International Conference on Dependability of Computer Systems, Brunów, Poland, 2009. 237–244

  33. Lee D, Na J. A novel simulation fault injection method for dependability analysis. IEEE Des Test Comput, 2009, 26: 50–61

    Article  Google Scholar 

  34. Wunderlich H, Holst S. Generalized fault modeling for logic diagnosis. In: Models in Hardware Testing. New York: Springer, 2009. 133–155

    Google Scholar 

  35. Di Natale G, Doulcier M, Flottes M L, et al. Self-test techniques for crypto-devices. IEEE Trans VLSI Syst, 2010, 18: 329–333

    Article  Google Scholar 

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Authors and Affiliations

  1. Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Stuttgart, D-70569, Germany

    Rafal Baranowski, Nadereh Hatami, Michael E. Imhof, Michael A. Kochte, Hans-Joachim Wunderlich & Christian G. Zoellin

  2. Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino TO, I-10129, Italy

    Stefano Di Carlo, Nadereh Hatami & Paolo Prinetto

Authors
  1. Rafal Baranowski
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  2. Stefano Di Carlo
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  3. Nadereh Hatami
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  4. Michael E. Imhof
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  5. Michael A. Kochte
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  6. Paolo Prinetto
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  7. Hans-Joachim Wunderlich
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  8. Christian G. Zoellin
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Correspondence to Rafal Baranowski.

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Baranowski, R., Di Carlo, S., Hatami, N. et al. Efficient multi-level fault simulation of HW/SW systems for structural faults. Sci. China Inf. Sci. 54, 1784–1796 (2011). https://doi.org/10.1007/s11432-011-4366-9

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  • DOI: https://doi.org/10.1007/s11432-011-4366-9

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