Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

Advertisement

Springer Nature Link
Log in

Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm2. The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is −1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is −121.5 dBc/Hz with a 1 MHz offset.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21

Similar content being viewed by others

References

  1. IEEE Draft Standard for Information technology. (2010). Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs). P802.15.4g/D2, October 2010.

  2. Perrott, M. H., Tewksbury, T. L., III, & Sodini, C. G. (1997). A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation. IEEE Journal of Solid-State Circuits, 32(12), 2048–2060.

    Article  Google Scholar 

  3. Kratyuk, V., Hanumolu, P. K., Moon, U. K., & Mayaram, K. (2007). A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy. IEEE Transactions on Circuits and Systems II, 54(3), 247–251.

    Article  Google Scholar 

  4. Dudek, P., Szczepanski, S., & Hatfield, J. V. (2000). A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line. IEEE Journal of Solid-State Circuits, 35(2), 240–247.

    Article  Google Scholar 

  5. Staszewski, R. B., & Balsara, P. T. (2005). Phase-domain all-digital phase-locked loop. IEEE Transactions on Circuits System II, Express Briefs, 52(3), 159–163.

    Article  Google Scholar 

  6. Lee, M., & Abidi, A. A. (2008). A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue. IEEE Journal of Solid-State Circuits, 43(4), 769–777.

    Article  Google Scholar 

  7. Henzler, S., Koepp, S., Lorenz, D., Kamp, W., Kuenemund, R., & Schmitt-Landsiedel, D. (2008). A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion. IEEE Journal of Solid-State Circuits, 43(7), 1666–1676.

    Article  Google Scholar 

  8. Lu, L., Hsieh, H., & Liao, Y. (2006). A wide tuning-range CMOS VCO with a differential tunable active inductor. IEEE Transactions on Microwave Theory and Techniques, 3, 3462–3468.

    Article  Google Scholar 

  9. Yoo, S.-S., Choi, Y.-C., Song, H.-J., Park, S.-C., Park, J.-H., & Yoo, H.-J. (2011). A 5.8-GHz high-frequency resolution digitally controlled oscillator using the difference between inversion and accumulation mode capacitance of pMOS varactors. IEEE Transactions on Microwave Theory and Techniques, 59(2), 375–382.

    Article  Google Scholar 

  10. Hsu, C.-M., Strayer, M. Z., & Perrott, M. H. (2008). A low-noise, wide-BW 3.6 GHz digital fractional-N synthesizer with a noise-shaping time-to digital converter and quantization noise cancellation. IEEE Journal of Solid-State Circuits, 43(12), 2776–2786.

    Article  Google Scholar 

  11. Kratyuk, V., Hanumolu, P. K., Ok, K., Moon, U.-K., & Mayaram, K. (2009). A digital PLL with a stochastic time-to-digital converter. IEEE Transactions on Circuits System I, 56(8), 1612–1621.

    Article  MathSciNet  Google Scholar 

  12. Seo, Y.-H., Lee, S.-K., & Sim, J.-Y. (2011). A 1-GHz digital PLL With a 3-ps resolution floating-point-number TDC in a 0.18- CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), 70–74.

    Article  Google Scholar 

  13. Liao, K.-C., Huang, P.-S, Chiu, W.-H., & Lin, T.-H. (2009). A 400-MHz/900-MHz/2.4-GHz multi-band FSK transmitter in 0.18-μm CMOS. In Proceedings of Asian Solid-State Circuits Conference, pp. 353–356, November, 2009.

  14. Ferriss, M. A., & Flynn, M. P. (2008). A 14 mW fractional-N PLL modulator with a digital phase detector and frequency switching scheme. IEEE Journal of Solid-State Circuits, 43(11), 2464–2471.

    Article  Google Scholar 

  15. Liu, Y. H., & Lin, T. H. (2007). An energy-efficient 1.5-Mbps wireless FSK transmitter with a ΣΔ-modulated phase rotator. In Proceedings of European Solid-State Circuits Conference, pp. 488–491, September, 2007.

  16. Jacobs, P., Janssens, J., Geurts, T., & Crols, J. (2003). A 0.35 μm CMOS fractional-N transmitter for 315/433/868/915 MHz ISM Applications. In Proceedings of European Solid-State Circuits Conference, pp. 425–428, September, 2003.

  17. Quinlan, P., Crowley, P., Chanca, M., Hudson, S., Hunt, B., Mulvaney, K., et al. (2004). A multimode 0.3–200-kb/s transceiver for the 433/868/915-MHz bands in 0.25-μm CMOS. IEEE Journal of Solid-State Circuits, 39(12), 2297–2310.

    Article  Google Scholar 

  18. Analog Devices: Datasheet ADF7020, May 2005.

Download references

Acknowledgments

This work was supported by the IT R&D program of MKE/KEIT [10035236-2012-03, development of wireless system for smart utility network.

Author information

Authors and Affiliations

  1. College of Information and Communication Engineering, Sungkyunkwan University, 2066, Seobu-ro, Jangan-gu, Suwon, Gyeonggi-do, 440-746, Korea

    Hongjin Kim, SoYoung Kim & Kang-Yoon Lee

Authors
  1. Hongjin Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. SoYoung Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Kang-Yoon Lee
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Kang-Yoon Lee.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kim, H., Kim, S. & Lee, KY. Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application. Analog Integr Circ Sig Process 74, 599–612 (2013). https://doi.org/10.1007/s10470-012-0020-8

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-012-0020-8

Keywords

Search

Navigation