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Accurate delay models of CMOS CML circuits for design optimization

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Abstract

This paper presents accurate delay models of current-mode logic (CML) circuits for equation-based circuit optimization. We propose accurate edge-rate-dependent delay models of a CML buffer, a latch, and a multiplexer. Newly proposed delay models have compatibility with geometric programming and scalability for the hierarchical design of CML-based circuits, thereby enabling true constraint-driven equation-based design optimization. In order to validate these models, we show the modeling errors of unit CML gates over a wide range of delay and edge rates. N-stage CML buffers and a 28 Gb/s serializer in 45 nm CMOS technology are optimized for minimum power dissipation. The numerical experiments indicates that the proposed delay models can guarantee the intended operation of CML-based circuits when used in the equation-based design optimization.

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Acknowledgments

This paper was supported by Faculty Research Fund, Sungkyunkwan University, 2013.

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Authors and Affiliations

  1. College of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea

    Ikchan Jang & SoYoung Kim

  2. Department of Electronics Engineering, Konkuk University, Seoul, Korea

    Jintae Kim

Authors
  1. Ikchan Jang
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  2. Jintae Kim
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  3. SoYoung Kim
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Correspondence to SoYoung Kim.

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Jang, I., Kim, J. & Kim, S. Accurate delay models of CMOS CML circuits for design optimization. Analog Integr Circ Sig Process 82, 297–307 (2015). https://doi.org/10.1007/s10470-014-0460-4

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  • DOI: https://doi.org/10.1007/s10470-014-0460-4

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