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A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS

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Abstract

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds for the remaining 4 LSBs. The DAC capacitance at the front-end remains small enough to achieve high sampling rate with increased input bandwidth. Two asynchronously clocked alternate comparators are used additionally to improve conversion speed. The ADC is designed and simulated in 28 nm FD-SOI CMOS. It consumes 4.1 mW from a 1 V supply, while achieving a SNDR of 52.1 dB and a Figure-of-Merit of 11.4 fJ/conversion-step.

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References

  1. Murmann, B., Nikaeen, P., Connelly, D. J., & Dutton, R. W. (2006). Impact of scaling on analog performance and associated modeling needs. IEEE Transactions on Electron Devices, 53(9), 1.

    Article  Google Scholar 

  2. Chen, S. W. M., & Brodersen, R. W. (2006). A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13\(\mu\)m. IEEE Journal of Solid-State Circuits, 41(12), 2669–2680.

    Article  Google Scholar 

  3. Jiang, T., Liu, W., Zhong, F. Y., Zhong, C., Hu, K., & Chiang, P. Y. (2012). A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive approximation ADC with improved feedback delay in 40-nm CMOS. IEEE Journal of Solid-State Circuits, 47, 2444–2453.

    Article  Google Scholar 

  4. Liu, C. -C., Chang, S. -J., Huang, G. -Y., & Lin, Y. -Z. (2010). A 10 bit 50 MS/s SAR ADC with a monotonic capacitor switching procedure. Journal of Solid State Circuits, 45(4), 731–740.

    Article  Google Scholar 

  5. Kull, L., Toifl, T., Schmatz, M., Francese, P. A., Menolfi, C., Braendli, M., et al. (2013). A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. IEEE Journal of Solid-State Circuits, 48(12), 3049–3058.

    Article  Google Scholar 

  6. Kilic, M., Leblebici, Y. (2017). A DAC assisted speed enhancement technique for high resolution SAR ADC. PRIME 2017, Taormina, Italy.

  7. Nuzzo, P., Nani, C., Armiento, C., Sangiovanni-Vincentelli, A., Craninckx, J., & Van der Plas, G. (2012). A 6-Bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(1), 80–92.

    Article  MathSciNet  Google Scholar 

  8. Razavi, B. (2015). The bootstrapped switch [a circuit for all seasons]. IEEE Solid-State Circuits Magazine, 7(3), 1215.

    Google Scholar 

  9. Schinkel, D., Mensink, E., Klumperink, E., van Tuijl, E., Nauta, B. (February 2007). A double-tail latch-type voltage sense amplifier with 18ps setup+hold time. In 2007 IEEE international solid-state circuits conference digest of technical papers (pp 314–315).

  10. Sun, G., Zhang, Y., He, L., Zhu, X. (2014). A threshold control technique for CMOS comparator design. In 2014 IEEE international conference on electron devices and solid-state circuits.

  11. Miyahara, M., Asada, Y., Paik, D., Matsuzawa, A. (2008). A low-noise self-calibrating dynamic comparator for high-speed ADCs. In Proceedings IEEE asian solid-state circuits conference (pp. 269–272).

  12. Hong, H. K., Kang, H. W., Sung, B., Lee, C. H., Choi, M., Park, H. J., Ryu, S. T. (2013). An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. In 2013 IEEE international solid-state circuits conference digest of technical papers (pp. 470–471).

  13. Fang, J., Thirunakkarasu, S., Yu, X., Silva-Rivas, F., Zhang, C., Singor, F., et al. (2017). A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS. IEEE Transactions on Circuits and Systems I, 64, 1673–1683.

    Article  Google Scholar 

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Authors and Affiliations

  1. Microelectronic Systems Laboratory, Swiss Federal Institute of Technology, Lausanne, 1015, Lausanne, Switzerland

    Mustafa Kilic & Yusuf Leblebici

  2. Centre Suisse d’Electronique et de Microtechnique, Zurich, Switzerland

    Themistoklis G. Mavrogordatos

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  1. Mustafa Kilic
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  2. Themistoklis G. Mavrogordatos
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  3. Yusuf Leblebici
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Correspondence to Mustafa Kilic.

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Kilic, M., Mavrogordatos, T.G. & Leblebici, Y. A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS. Analog Integr Circ Sig Process 97, 397–404 (2018). https://doi.org/10.1007/s10470-018-1222-5

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  • DOI: https://doi.org/10.1007/s10470-018-1222-5

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