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An implementation of matrix–matrix multiplication on the Intel KNL processor with AVX-512

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Abstract

The second generation Intel Xeon Phi processor codenamed Knights Landing (KNL) have recently emerged with 2D tile mesh architecture and the Intel AVX-512 instructions. However, it is very difficult for general users to get the maximum performance from the new architecture since they are not familiar with optimal cache reuse, efficient vectorization, and assembly language. In this paper, we illustrate several developing strategies to achieve good performance with C programming language by carrying out general matrix–matrix multiplications and without the use of assembly language. Our implementation of matrix–matrix multiplication is based on blocked matrix multiplication as an optimization technique that improves data reuse. We use data prefetching, loop unrolling, and the Intel AVX-512 to optimize the blocked matrix multiplications. When we use a single core of the KNL, our implementation achieves up to 98% of SGEMM and 99% of DGEMM using the Intel MKL, which is the current state-of-the-art library. Our implementation of the parallel DGEMM using all 68 cores of the KNL achieves up to 90% of DGEMM using the Intel MKL.

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Acknowledgements

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. NRF-2015M3C4A7075662).

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  1. Soongsil University, Seoul, 06978, Korea

    Roktaek Lim, Yeongha Lee, Raehyun Kim & Jaeyoung Choi

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  1. Roktaek Lim
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  2. Yeongha Lee
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Correspondence to Jaeyoung Choi.

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Lim, R., Lee, Y., Kim, R. et al. An implementation of matrix–matrix multiplication on the Intel KNL processor with AVX-512. Cluster Comput 21, 1785–1795 (2018). https://doi.org/10.1007/s10586-018-2810-y

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  • DOI: https://doi.org/10.1007/s10586-018-2810-y

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