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Synthesis and Time Partitioning for Reconfigurable Systems

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Abstract

This paper aims to introduce a time partitioning algorithm which is an important step during the design process for fully reconfigurable systems. This algorithm is used to solve the time partitioning problem. It divides the input task graph model to an optimal number of partitions and puts each task in the appropriate partition so that the latency of the input task graph is optimal. Also a part of this paper is consecrated for implementation of some examples on a fully reconfigurable architecture following our approach.

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Authors and Affiliations

  1. Faculty of Sciences of Monastir, Laboratory of Electronics and Micro-Electronics (EμE), 5000, Monastir, Tunisia

    B. Ouni & A. Mtibaa

  2. C.E.S, National Engineering School of Sfax, (ENIS), B.P. W. 3038, Sfax, Tunisia

    M. Abid

Authors
  1. B. Ouni
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  2. A. Mtibaa
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  3. M. Abid
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Correspondence to A. Mtibaa.

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Ouni, B., Mtibaa, A. & Abid, M. Synthesis and Time Partitioning for Reconfigurable Systems. Des Autom Embed Syst 9, 177–191 (2004). https://doi.org/10.1007/s10617-005-1196-2

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  • DOI: https://doi.org/10.1007/s10617-005-1196-2

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