Abstract
The paper describes the implementation of a novel Analog-to-Digital-Converter (ADC) test technique for next generation low cost massive parallel ADC testing using a Field Programmable Gate Array (FPGA) on tester load board. The goal is to test the ADC which is embedded in an automotive micro controller with only pure digital tester sources. Therefore, the analog test stimulus for the ADC is generated by using ΔΣ-modulation technique off-line and analog filtering on load board. The digital test response is analyzed by a FPGA in real time by comparing the measured data with a reference signal. The modular concept of FPGA evaluation allows for quick and flexible reaction on changing production test requirements. Simply by reprogramming the FPGA with a new module there is no need of any hardware reconfigurations. Measurements with a high precision reference ADC in laboratory environment show that the method is ready for production.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
B. Dufort and G.W. Roberts, “On-Chip Analog Signal Generation for Mixed-Signal Built-In Self-Test,” IEEE Journal of Solid-State-Circuits, vol. 34, pp. 318–330, March 1999.
T. Homorodi and R. Martin, “High Parallelism Memory Test Advances based on MicroSpring Contact Technology,” Southwest Test Workshop, 2001.
“IEEE Standards for Terminology and Test Methods for Analog-to-Digital Converters,” The Institute of Electrical and Electronics Engineers, Inc., ISBN 0-7381-2724-8, 2000.
A. Lechner and A. Richardson, “Test of A/D Converters,” in J.L. Huertas (ed), Test and Design-for-Testability in Mixed-Signal Integrated Circuits, Kluwer, 2004.
M. Mahoney, “DSP-Based Testing of Analog and Mixed-Signal Circuits,” IEEE Computer Society, Los Alamitos, California, ISBN 0-8186-0785-8, 1987.
H. Mattes, S. Sattler, and C. Dworski, “Controlled Sine Wave Fitting for ADC Test,” International Test Conference (ITC), pp. 963–971, 2004.
S.R. Norsworthy, R. Schreier, and G.C. Temes, “Delta–Sigma Data Converters—Theory, Design, and Simulation,” IEEE, Piscataway, New Jersey, ISBN 0-7803-1045-4, 1997.
G. Prenat, S. Mir, D. Vazquez, and L. Rolindez, “A Low-Cost Digital Frequency Testing Approach for Mixed-Signal Devices Using SD Modulation,” 10th International Mixed-Signals Testing Workshop (IMSTW), pp. 107–115, 2004.
TER Teradyne Inc. 1994–2004, http://www.teradyne.com.
“Test and Test Equipment,” International Technology Roadmap for Semiconductors (ITRS), 2004, http://www.itrs.net/Common/2004Update/ 2004Update.htm.
B. West, “Simultaneous Bidirectional Test Data Flow for a Low-Cost Wafer Test Strategy,” International Test Conference (ITC), pp. 947–951, 2003.
Z. Yu, D. Chen, and R. Geiger, “A Computationally Efficient Method for Accurate Spectral Testing Requiring Coherent Sampling,” International Test Conference (ITC), pp. 1398–1407, 2004.
Xilinx Inc.—the Programmable Logic Company™, http://www.xilinx.com, 1994–2005.
Author information
Authors and Affiliations
Corresponding author
Additional information
Editor: A. Richardson
Rights and permissions
About this article
Cite this article
Mattes, H., Kirmser, S. & Sattler, S. Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation. J Electron Test 22, 337–350 (2006). https://doi.org/10.1007/s10836-006-9501-y
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-006-9501-y