Abstract
Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs are introduced, which exploit a transition detector for timing error detection along with asynchronous local error correction schemes to provide timing error tolerance. The proposed, the Razor and the Time Dilation techniques were applied separately in the design of three versions of a 32-bit MIPS microprocessor core and the pci_bridge32 IWLS05 core, using a 90 nm CMOS technology. Comparisons based on simulation results validate the efficiency of the new design approach.
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Responsible Editor: M. Violante
This research has been co-funded by the European Union (European Social Fund) and Greek national resources under the framework of the “Thales” project of the “Education & Lifelong Learning” Operational Program.
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Valadimas, S., Tsiatouhas, Y., Arapoyanni, A. et al. Effective Timing Error Tolerance in Flip-Flop Based Core Designs. J Electron Test 29, 795–804 (2013). https://doi.org/10.1007/s10836-013-5419-3
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DOI: https://doi.org/10.1007/s10836-013-5419-3