Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content
Springer Nature Link
Log in

CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Parallel computing is widely utilized to speed up automatic test pattern generation (ATPG); however, most of today’s parallel ATPGs are non-deterministic, which often leads to non-reproducible test pattern sets. This paper presents a fault-parallel test pattern generator: CPP-ATPG; it generates the same test pattern set regardless of the thread count and timing. Besides, it exhibits good speedup scalability as the thread count increases. These are achieved by the circular pipeline processing (CPP) principle, which guides the proposed parallel ATPG to preserve the task processing orders that are necessary to ensure ATPG determinism but with low inter-thread synchronization overhead. Furthermore, a multi-round test generation and compaction strategy is proposed to avoid possible test pattern inflation. Experimental results show that CPP-ATPG exhibits close-to-linear speedup for at least up to 12 threads.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

References

  1. Aquado M, de la Torre E, Miranda M, Lopez-Barrio C (1993) Distributed implementation of an ATPG system using dynamic fault allocation. In: Proc. IEEE Int. test conf., pp 409–418

  2. Butenhof DR (1997) Programming with POSIX threads. Addison-Wesley Longman Publishing Co. Inc.

  3. Butler R, Keller B, Paliwal S, Scchoonover R, Swenton J (2000) Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. In: Proc. IEEE int. test conf., pp 530–537

  4. Cai X, Wohl P, Waicukausi J, Notiyath P (2010) Highly efficient parallel ATPG based on shared memory. In: Proc. IEEE int. test conf., pp 1–7

  5. Cai X, Wohl P (2013) A distributed-multicore hybrid atpg system. In: Proc. IEEE int. test conf., pp 1–7

  6. Cai X, Wohl P, Martin D (2014) Fault sharing in a copy-on-write based atpg system. In: Proc. IEEE int. test conf., pp 1–8

  7. Czutro A, Polian I, Lewis M, Engelke P, Reddy SM, Becker B (2009) TIGUAN: thread-parallel integration test pattern generator utilizing satisfiability analysis. In: Proc. IEEE vlsi des., pp 227–232

  8. Klenke RH, Aylor JH (1992) Parallel-processing techniques for automatic test pattern generation. IEEE Trans Comput 25(1):71–84

    Google Scholar 

  9. Klenke RH, Kaufman L, Aylor JH, Waxman R, Narayan P (1993) Workstation based parallel test generation. In: Proc. IEEE int. test conf., pp 419–428

  10. Ku JCY, Huang RH-M, Lin LYZ, Wen CH-P (2014) Suppressing test inflation in shared-memory parallel automatic test pattern generation. In: Proc. IEEE Asia South Pacific des. autom. conf., pp 664–669

  11. Liao K-Y, Chang C-Y, Li JC-M (2011) A parallel test pattern generation algorithm to meet multiple quality objectives. IEEE Trans Comput -Aided Des Integr Circuits Syst 30(11):1767–1772

    Article  Google Scholar 

  12. Patil S, Banerjee P (1989) A parallel branch-and-bound algorithm for test generation. In: Proc. IEEE DAC, pp 339–344

  13. Patil S, Banerjee P (1989) Fault partitioning issues in an integrated parallel test generation/fault simulation environment. In: Proc. IEEE int. test conf., pp 718–726

  14. Patil S, Banerjee P (1991) Performance trade-offs in a parallel test generation/fault simulation environment. IEEE Trans Comput-Aided Des Integr Circuits Syst 10(12):1542–1558

    Article  Google Scholar 

  15. Pomeranz I, Reddy LN (1993) COMPACTEST: a method to generate compact test sets for combinational circuits. IEEE Trans Comput -Aided Des Integr Circuits Syst 12(7):1040–1049

    Article  Google Scholar 

  16. Sehsu S (1965) On improved diganosis program. IEEE Trans Electron Comput 14(1):76–79

    Google Scholar 

  17. Sienicki J, Bushnell ML, Agrawal P, Agrawal VD (1995) An adaptive distributed algorithm for sequential circuit test generation. In: Proc. IEEE EURO-DAC, pp 236–241

  18. Waicukauski JA, Eichelberger EB, Forlenza DO, Lindbloom E, McCarthy T (1985) Fault simulation for structured vlsi. In: Proc. IEEE vlsi syst. des., pp 20–32

  19. Wolf JM, Kaufman LM, Klenke RH, Aylor JH, Waxman R (1996) An analysis of fault partitioned parallel test generation. IEEE Trans Comput-Aided Des Integr Circuits Syst 15(5):517–534

    Article  Google Scholar 

  20. Yeh K-W, Wu M-F, Huang J-L (2009) A low communication and load balanced parallel ATPG with improved static fault partition method. In: Proc. Int. conf. algorithms architectures parallel process, pp 362–371

  21. Yeh K-W, Huang J-L, Chao H-J, Wang L-T (2013) A circular pipeline processing based deterministic parallel test pattern generator. In: Proc. IEEE int. test conf., pp 1–8

Download references

Author information

Authors and Affiliations

  1. Graduate Institute of Electronics Engineering (GIEE), National Taiwan University, Taipei, 10617, Taiwan

    Kuen-Wei Yeh, Jiun-Lang Huang & Laung-Terng Wang

  2. Department of Electrical Engineering, National Taiwan University, Taipei, 10617, Taiwan

    Jiun-Lang Huang & Laung-Terng Wang

  3. SynTest Technologies, Inc., Sunnyvale, CA, 94086, USA

    Laung-Terng Wang

Authors
  1. Kuen-Wei Yeh
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jiun-Lang Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Laung-Terng Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Kuen-Wei Yeh.

Additional information

Responsible Editor: M. S. Abadir

Part of the manuscript was published in the Proceedings of International Test Conference, 2013 [21].

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yeh, KW., Huang, JL. & Wang, LT. CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. J Electron Test 32, 625–638 (2016). https://doi.org/10.1007/s10836-016-5615-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-016-5615-z

Keywords

Search

Navigation