Abstract
The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoC). This paper highlights problematic aspects of a Burn-In flow and describes a two-layered adaptive technique that permits to optimize the stress application and strongly reduce BI test time. At the SoC level, the described methodology adaptively copes with FLASH erase time uncertainties; at the Automatic Test Equipment (ATE) level, the strategy relies on power monitors and tester intelligence. The paper reports experimental results on a SoC manufactured by STMicroelectronics; figures show an optimized usage of stress resources and demonstrates a reduction of 25% in the BI test time when using the proposed adaptive techniques.
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Appello, D., Bernardi, P., Bugeja, C. et al. Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC. J Electron Test 34, 43–52 (2018). https://doi.org/10.1007/s10836-018-5705-1
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DOI: https://doi.org/10.1007/s10836-018-5705-1