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Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems

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Abstract

In this paper, we present an analytical methodology to measure the vulnerability of the memory components of a microprocessor-based computing system. It is based on the data and the instruction lifetime and residence. The proposed approach considers only the software-layer of the system, which makes it usable at early design stage when the hardware architecture is not fully defined. Then, to consider the hardware memory hierarchy (i.e., RAM, Caches, Register Files) at software level, we have developed a memory subsystem emulator that can be easily configured to support different features. The methodology can be used to perform a fast, easy and not costly cache-aware Design Space Exploration (DSE) to accurately evaluate the vulnerability of the RAM and the caches. The first set of experiments run on Mibench benchmarks shows that we can perform a fast, easy and not costly DSE to accurately evaluate the effects of the faults in both the RAM and the caches. In addition, we validate the proposed approach on a real industrial test case, which is a Flight Management System for avionic application. The results show that the proposed methodology give precise results compared to a classical fault injection tool, and it scales well with the complexity of the application.

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Authors and Affiliations

  1. CEA, LETI, University Grenoble Alpes, F-38000, Grenoble, France

    Maha Kooli

  2. CNRS, Grenoble INP, TIMA, University Grenoble Alpes, 38000, Grenoble, France

    Giorgio Di Natale

  3. Ecole Centrale de Lyon, Lyon Institute of Nanotechnology, Lyon, France

    Alberto Bosio

Authors
  1. Maha Kooli
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  2. Giorgio Di Natale
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  3. Alberto Bosio
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Correspondence to Maha Kooli.

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Responsible Editor: S. Hamdioui

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Kooli, M., Di Natale, G. & Bosio, A. Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems. J Electron Test 35, 145–162 (2019). https://doi.org/10.1007/s10836-019-05785-0

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