This issue carries ten articles, including three JETTA Letters. They cover thermal effects, fault tolerance, verification and debugging, resistive faults, hardware Trojan, network-on-chip (NoC) testing, planar magnetic measurement, digital bus repeater, and aging due to bias temperature instability (BTI). Parts of the third and fourth papers first appeared at the Nineteenth IEEE Latin American Test Symposium (LATS) held during March 12–16, 2018 in Sao Paolo, Brazil.

Authors of the first paper are Rakesh Kumar and Shreekrishna Kumar from Mahatma Gandhi University, Kottayam, Kerala, India. They present a multilayer flexible printed circuit board (PCB) structure and devise a thermal management system for it. The PCB contains a heat conduction plane. Thermal analysis shows that the cooling plan must take the folding of the PCB into account.

The second paper discusses a memory subsystem emulator for architectural exploration of a processor system for vulnerability to errors due to memory faults. An avionics application serves as illustration. The authors are Kooli and Di Natale from University of Grenoble Alpes, Grenoble, France, and Bosio from Ecole Centrale de Lyon, Lyon, France.

The third paper develops algorithms for computing probabilities of propagating single event transients (SET) through a digital circuit. A probability matrix procedure accounts for the fault masking due to signal correlations or when the SET remains active through multiple clock cycles. Contributors of this work are Cai, Wang, Yu and He from Changsha University of Science and Technology, Changsha,China.

Authors of the fourth paper are Kourfali and Stroobandt from Ghent University, Ghent, Belgium, Fricke from Ruhr University of Bochum, Bochum, Germany, and Huebner from Technical University of Cottbus - Senftenberg, Senftenberg, Germany. They address the problem of verification for FPGA-based design. CAD tools support their integration of a debugging infrastructure into the design.

Cardoso Medeiros, Brum and Bolzani Poehls from Pontifical Catholic University of Rio Grande do Sul – PUCRS, Porto Alegre, Brazil, and Copetti and Balen from Federal University of Rio Grande do Sul – UFRGS, Porto Alegre, Brazil, discuss faults of the FinFET-based SRAM in the next paper. This study examines manufacturing defects of FinFET devices, such as weak resistive-open and weak resistive-bridge, for their influence on the temperature and behavior of the memory cell.

Next, Ranjbar, Bayat-Sarmadi, Pooyan and Asadi from Sharif University of Technology, Tehran, Iran, present a Trojan detection method for SRAM-based FPGAs. Their test can detect a Trojan as well as distinguish it from a hardware fault. Although, the testability overhead more than doubles the size of the circuit, it remains significantly lower than that for the triple modular redundancy (TMR).

The seventh paper presents a solution for the test of communication channels of a network-on-chip (NoC) device. A built-in self-test detects and locates all stuck-at faults of the network. The solution of a graph color problem provides a test schedule that minimizes the test time. An experiment shows scalability of test time with respect to the network size. Contributors of this work are Bhowmik from Indian Institute of Information Technology, Bhagalpur, India, Biswas and Deka from Indian Institute of Technology Guwahati, India, and Bhattacharya from Indian Institute of Technology Kharagpur, India.

Finally, three JETTA Letters complete this issue. In the first Letter, Oumar, Boukhari, Taha, Capraro, Pietroy, Chatelon and Rousseau from University of Lyon, Saint-Etienne, France, describe measurement techniques for integrated transformers fabricated on a planar magnetic substrate.

In the second Letter, Omaña, Govindaraj and Metra from Universityof Bologna, Bologna, Italy address the problem of reducing the propagation delay on a digital bus. They propose the use of repeaters similar to the buffer used for driving a large capacitive load (e.g., a large fanout) in a digital logic circuit. Their repeater consists of a chain of inverters of progressively increasing sizes.

Grossi and Omaña from University of Bologna, Bologna, Italy, are the authors of the third Letter. They compute the clock skew generated by the aging of buffers due to bias temperature instability (BTI) and propose slowing the clock down appropriately over the lifetime of the circuit.