Abstract
A fractional-N phase-locked loop (PLL) with four kinds of delta-sigma modulators (DSMs), is implemented to analyze and compare PLL phase noise and fractional spur performances among different DSMs, including 4th- and 5th-order single-loop (SL) and 3rd- and 4th-order multi-stage noise-shaping (MASH) ones. SL-DSMs with fewer output levels resulting in smaller instantaneous phase error, achieve better phase noise. MASH DSMs with wider quantization levels having more efficient randomization and dithering effects, generate less fractional spur. Experimental results show that in-band and out-of-band fractional spurs of MASH DSM are 10.5 and 5.8dB better than those of SL-DSM, respectively, while out-of-band phase noise of SL-DSM is 4.5dB lower than that of MASH DSM, with the same order. The fractional-N PLL is fabricated in 180nm CMOS with a 1.8V supply voltage and power consumption of approximately 23mW.
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References
Arora H, Klemmer N, Morizio JC, Wolf PD (2005) Enhanced phase noise modeling of fractional-N frequency synthesizers. IEEE Trans Circuits Syst I(TCASI) 52(2):379–395
Li CJ, Huang CH, Ho WH, Horng TS (2006) Incorporating the single-loop delta-sigma modulator in fractional-N frequency synthesizer for phase-noise improvement. In: Proc. IEEE European microwave integrated circuits conference (EMICC). Manchester, pp 183–186
Reddy A (2007) Noise shaping with sigma delta modulators in fractional-N synthesizers. In: Proc. IEEE radio-frequency integration technology (RFIT). Rasa Sentosa Resort, pp 329–332
Rhee W, Song BS (2000) A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator. IEEE J Solid-State Circ (JSSC) 35(10):1453–1460
Rhee W, Xu N, Zhou B, Wang Z (2013) Fractional-N frequency synthesis: overview and practical aspects with FIR-embedded design. J Semicond Technol Sci (JSTS) 13(2):170–183
Sadatnejad N, Miar-Naimi H (2015) A new fractional spur modeling in fractional-N frequency synthesizers. In: Proc. IEEE Canadian conference on electrical and computer engineering (CCECE). Halifax, pp 536–540
Song J, Park IC (2010) Spur-free MASH delta-sigma modulation. IEEE Trans Circ Syst I(TCASI) 57 (9):2426–2437
Song J (2015) Hardware reduction of MASH delta-sigma modulator based on partially folded architecture. IEEE Trans Circuits Syst II(TCASII) 62(10):967–971
Yu X, Sun Y, Rhee W, et al. (2009) A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order ΔΣ modulation and weighted FIR filtering. In: Proc. IEEE Asian solid-state circuits conference (A-SSCC). Taipei, pp 77–80
Yu X, Sun Y, Rhee W, Wang Z (2009) A ΔΣ fractional-N synthesizer with customized noise shaping for WCDM/HSDPA applications. IEEE J Solid-State Circ (JSSC) 44 (8):2193–2201
Acknowledgements
This work was supported in part by Professor Woogeun Rhee at Tsinghua University and the National Natural Science Foundation of China (No. 61674014 and No. 61620106001).
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Zhou, B., Li, Y. & Zhao, F. Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs. J Electron Test 35, 917–923 (2019). https://doi.org/10.1007/s10836-019-05839-3
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DOI: https://doi.org/10.1007/s10836-019-05839-3