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Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables

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Abstract

In this paper, we have achieved run-time dynamic reconfiguration by employing a category of logic cells equipped to realize programmability in Cellular Automata (CA) architectures on Field Programmable Gate Arrays (FPGAs). This is essential for real time VLSI implementations of random number generators, whose functionality requires reconfiguration during run-time, and are called Programmable CA (PCA). The logic cells realizing the PCA are amongst a subset of Look-Up Tables (LUTs) offered by Xilinx FPGAs, known as CFGLUT5. Programmability involves scanning out the contents of the truth-table (TT) originally configuring these LUTs and reconfiguring it with a modified functionality. This feature additionally aids testability which allows to carry out an equality check of the scanned output with a golden copy of the TT contents originally configuring the LUTs during design deployment. Vacant inputs in the LUTs realizing the PCA have been used to establish different scan path arrangements through flip-flops for exercising testability and fault localization further. The entire design flow resulted in a no logic overhead scenario compared to where scan paths did not exist. Any physical FPGA slice coordinate housing a faulty logic element, can be suitably bypassed for future implementations on the same FPGA by applying appropriate placement constraints.

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Authors and Affiliations

  1. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, West Bengal, 721302, India

    Ayan Palchaudhuri & Anindya Sundar Dhar

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  1. Ayan Palchaudhuri
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  2. Anindya Sundar Dhar
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Correspondence to Ayan Palchaudhuri.

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Palchaudhuri, A., Dhar, A.S. Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables. J Electron Test 36, 519–536 (2020). https://doi.org/10.1007/s10836-020-05894-1

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