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Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

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Abstract

To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

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References

  1. Calin T, Nicolaidis M, Velazco R (1996) Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Trans Nucl Sci 43(6):2874–2878

    Article  Google Scholar 

  2. Eftaxiopoulos N, Axelos N, Pekmestzi K (2015) DONUT: A Double Node Upset Tolerant Latch. Proc. IEEE Annual Symposium on VLSI, Montpellier, France, pp 509–514

    Google Scholar 

  3. Eftaxiopoulos N, Axelos N, Zervakis G, Tsoumanis K, Pekmestzi K (2015) Delta DICE: A Double Node Upset Resilient Latch. Proc. IEEE International Midwest Symposium on Circuits and Systems, Fort Collins, USA, pp 1–4

    Google Scholar 

  4. Fazeli M, Miremadi S, Ejlali A, Patooghy A (2009) Low Energy Single Event Upset/Single Event Transient-Tolerant Latch for Deep Submicron Technologies. IET Comput Digital Tech 3(3):289–303

    Article  Google Scholar 

  5. Huang Z (2014) A High Performance SEU Tolerant Latch for Nanoscale CMOS Technology. Proc. IEEE Design Automation Test in Europe, Dresden, Germany, pp 1–5

    Google Scholar 

  6. Huang Z, Liang H, Hellebrand S (2015) A High Performance SEU Tolerant Latch. Journal of Electronics Testing 31:349–359

    Article  Google Scholar 

  7. Huang Z, Liang H, Hellebrand S (2015) A High Performance SNU Tolerant Latch. J Electron Test 31(4):349–359

    Article  Google Scholar 

  8. Hui X, Yun Z (2015) Circuit and Layout Combination Technique to Enhance Multiple Nodes Upset Tolerance in Latches. IEICE Electronics Express 12(9):1–7

    Article  Google Scholar 

  9. Jiang J, Xu Y, Ren J, Zhu W, Lin D, Xiao J, Kong W, Zou S (2018) Low-Cost Single Event Double-Upset Tolerant Latch Design. Electron Lett 54(9):554–556

    Article  Google Scholar 

  10. Katsarou K, Tsiatouhas Y (2014) Double Node Charge Sharing SEU Tolerant Latch Design,” Proc. IEEE International Symposium on On-Line Testing and Robust System Design, Platja d'Aro, Spain, pp. 122–127

  11. Katsarou K, Tsiatouhas Y (2015) Soft Error Interception Latch: Double Node Charge Sharing SNU Tolerant Design. Electron Lett 51(4):330–332

    Article  Google Scholar 

  12. Li Y, Wang H, Liu R, Chen L, Nofal I, Shi S, He A, Guo G, Baeg S, Wen S, Wong R, Chen M, Wu Q (2017) A Quatro-Based 65 nm Flip-Flop Circuit for Soft-Error Resilience. IEEE Trans Nucl Sci 64(6):1554–1561

  13. Li Y, Wang H, Liu R, Chen L, Nofal I, Chen Q, He A, Guo G, Baeg S, Wen S, Wong R, Wu Q, Chen M (2016) A 65 nm Temporally Hardened Flip-Flop Circuit. IEEE Trans Nucl Sci 63(6):2934–2940

    Article  Google Scholar 

  14. Li Y, Wang H, Yao S, Yan X, Gao Z, Xu J (2015) Double Node Upsets Hardened Latch Circuits. Journal of Electronics Testing 31:537–548

    Article  Google Scholar 

  15. Li H, Xiao L, Qi C (2019) High Robust and Cost Effective Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology. Microelectron Reliab 93:89–97

    Article  Google Scholar 

  16. Lin S, Kim Y, Lombardi F (2011) Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS. IEEE Transactions on Very Large Scale Integration VLSI Systems 19(7):1315–1319

    Article  Google Scholar 

  17. Lin D, Xu Y, Li X, Xie X, Jiang J, Ren J, Zhu H, Zhang Z, Zou S (2018) A Novel Self-Recoverable and Triple Nodes Upset Resilience DICE Latch. IEICE Electronics Express 15(19):1–10

    Article  Google Scholar 

  18. Mavis D, Eaton P (2007) SEU and SET Modeling and Mitigation in Deep Submicron Technologies. Proc. IEEE International Reliability Physics Symposium, Phoenix, USA, pp 293–305

    Google Scholar 

  19. Mitra S, Zhang M, Seifert N, Mak T, Kim K (2007) Built-in Soft Error Resilience for Robust System Design. Proc IEEE International Conference on IC Design and Technology, Austin, USA, pp. 1–6

  20. Namba K, Sakata M, Ito H (2010) Single Event Induced Double Node Upset Tolerant Latch. Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Kyoto, Japan, pp. 280–288

  21. Nan H, Choi K (2012) High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology. IEEE Trans Circuits Syst I Regul Pap 59(7):445–1457

    Article  MathSciNet  Google Scholar 

  22. Nan H, Choi K (2012) Low Cost and Highly Reliable Hardened Latch Design for Nanoscale CMOS Technology. Microelectron Reliab 52:1209–1214

    Article  Google Scholar 

  23. Omana M, Rossi D, Metra C (2010) High-Performance Robust Latches. IEEE Trans Comput 59(11):1455–1465

    Article  MathSciNet  Google Scholar 

  24. Peng C, Xiao S, Lu W, Zhang J, Wu X, Chen J, Lin Z (2018) Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application. IEEE Trans Very Large Scale Integr VLSI Syst 26(3):584–588

    Article  Google Scholar 

  25. Qi C, Xiao L, Guo J (2015) Low Cost and Highly Reliable Radiation Hardened Latch Design in 65 nm CMOS Technology. Microelectron Reliab 55:863–872

    Article  Google Scholar 

  26. Ramin R (2017) Single Event Double Node Upset Tolerance in MOS/Spintronic Sequential and Combinational Logic Circuits. Microelectron Reliab 69:109–114

    Article  Google Scholar 

  27. She X, Li N, Tong J (2012) SEU Tolerant Latch Based on Error Detection. IEEE Trans Nucl Sci 59(1):211–214

    Article  Google Scholar 

  28. Watkins A, Tragouodas S (2016) A Highly Robust Double Node Upset Tolerant Latch. Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Storrs, USA, pp. 15–20

  29. Watkins A, Tragouodas S (2017) Radiation Hardened Latch Designs for Double and Triple Node Upsets. IEEE Trans Emerg Top Comput 99:1–10

    Google Scholar 

  30. Yan A, Huang Z, Yi M, Xu X, Ouyang Y, Liang H (2017) “Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. IEEE Trans Very Large Scale Integr VLSI Syst 25(6):1978–1982

    Article  Google Scholar 

  31. Yan A, Lai L, Zhang Y, Cui J, Huang Z, Song J, Guo J, Wen X (2018) Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS. IEEE Trans Emerg Top Comput 99:1–14

    Google Scholar 

  32. Yan A, Liang H, Huang Z, Jiang C, Yi M (2015) A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology. IEICE Trans Electron 98(12):1171–1178

    Article  Google Scholar 

  33. Yan A, Wu Z, Lu L, Chen Z, Song J, Ying Z, Girard P, Wen X (2019) Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. Proc IEEE Asian Test Symposium, pp. 43–48, Kolkata, India

  34. Yan A, Wu Z, Lu L, Chen Z, Song J, Ying Z, Girard P, Wen X (2019) Radiation-Hardened 14T SRAM Bitcell with Speed and Power Optimized for Space Application. IEEE Trans Very Large Scale Integr VLSI Syst 27(2):407–415

    Article  Google Scholar 

  35. Yan A, Yang K, Huang Z, Zhang J, Cui J, Fang X, Yi M, Wen X (2019) A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application. IEEE Trans Circuits Syst II Express Briefs 66(2):287–291

    Article  Google Scholar 

  36. Zhang H, Liu Z, Jiang J, Xiao J, Zhang Z, Zou S (2020) High-Performance and Single Event Double-Upset-Immune Latch Design. Electron Lett 56(23):1243–1245

    Article  Google Scholar 

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Acknowledgements

The corresponding author is Tianming Ni. This work was supported in part by the National Natural Science Foundation of China under Grants 61974001, 61874156, and 61904001, and Anhui University Doctor Startup Fund (Y040435009). This research was also supported in part by the NSFC-JSPS Exchange Program under Grant 6201101398.

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Correspondence to Tianming Ni.

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Yan, A., Cao, A., Xu, Z. et al. Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications. J Electron Test 37, 489–502 (2021). https://doi.org/10.1007/s10836-021-05962-0

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  • DOI: https://doi.org/10.1007/s10836-021-05962-0

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