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A quantum physical design flow using ILP and graph drawing

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Abstract

Implementing large-scale quantum circuits is one of the challenges of quantum computing. One of the central challenges of accurately modeling the architecture of these circuits is to schedule a quantum application and generate the layout while taking into account the cost of communications and classical resources as well as the maximum exploitable parallelism. In this paper, we present and evaluate a design flow for arbitrary quantum circuits in ion trap technology. Our design flow consists of two parts. First, a scheduler takes a description of a circuit and finds the best order for the execution of its quantum gates using integer linear programming regarding the classical resources (qubits) and instruction dependencies. Then a layout generator receives the schedule produced by the scheduler and generates a layout for this circuit using a graph-drawing algorithm. Our experimental results show that the proposed flow decreases the average latency of quantum circuits by about 11 % for a set of attempted benchmarks and by about 9 % for another set of benchmarks compared with the best in literature.

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Notes

  1. \(C_{A}\) is an empty set in case of an uncontrolled gate.

  2. As Soon As Possible.

  3. As Late As Possible.

Abbreviations

CAD:

Computer Aided Design

ILP:

Integer Linear Programming

QASM:

Quantum Assembly

GDToolkit:

Graph Drawing Toolkit [1, 2]

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Acknowledgments

We would like to thank Mehdi Saeedi for his helpful discussion.

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Authors and Affiliations

  1. Computer Engineering and IT Department, Amirkabir University of Technology, Tehran, Iran

    Maryam Yazdani, Morteza Saheb Zamani & Mehdi Sedighi

Authors
  1. Maryam Yazdani
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  2. Morteza Saheb Zamani
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  3. Mehdi Sedighi
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Correspondence to Maryam Yazdani.

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Yazdani, M., Saheb Zamani, M. & Sedighi, M. A quantum physical design flow using ILP and graph drawing. Quantum Inf Process 12, 3239–3264 (2013). https://doi.org/10.1007/s11128-013-0597-6

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