Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

Quantum circuit physical design methodology with emphasis on physical synthesis

  • Published:
Quantum Information Processing Aims and scope Submit manuscript

Abstract

In our previous works, we have introduced the concept of “physical synthesis” as a method to consider the mutual effects of quantum circuit synthesis and physical design. While physical synthesis can involve various techniques to improve the characteristics of the resulting quantum circuit, we have proposed two techniques (namely gate exchanging and auxiliary qubit selection) to demonstrate the effectiveness of the physical synthesis. However, the previous contributions focused mainly on the physical synthesis concept, and the techniques were proposed only as a proof of concept. In this paper, we propose a methodological framework for physical synthesis that involves all previously proposed techniques along with a newly introduced one (called auxiliary qubit insertion). We will show that the entire flow can be seen as one monolithic methodology. The proposed methodology is analyzed using a large set of benchmarks. Experimental results show that the proposed methodology decreases the average latency of quantum circuits by about 36.81 % for the attempted benchmarks.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

Explore related subjects

Discover the latest articles, news and stories from top researchers in related subjects.

References

  1. http://www.itrs.net/Links/2010ITRS/Home2010.htm

  2. Feynman, R.P.: Quantum mechanical computers. Found. Phys. 16, 507–531 (1986)

    Google Scholar 

  3. Shor, P.: Polynomial time algorithms for prime factorization and discrete logarithms on a quantum computer. SIAM J. Comput. 26(5), 1484–1509 (1997)

    Article  MathSciNet  MATH  Google Scholar 

  4. Grover, L.: A Fast Quantum mechanical algorithm for database search. In: Proceeding of ACM Symposium on Theory of Computing, pp. 212–219 (1996)

  5. Ohya, M.: Quantum algorithm for SAT problem and quantum mutual entropy. In: Proceedings of the Von Neumann Centennial Conference, pp. 109–138 (2003)

  6. Marinescu, D.C., Marinescu, G.M.: Approaching Quantum Computing. Prentice Hall, Upper Saddle River (2005)

    Google Scholar 

  7. Spiller, T.P., et al.: An introduction to quantum information processing: applications and realizations. Contemp. Phys. 46(6), 407–436 (2005)

    Article  ADS  Google Scholar 

  8. Nakahara, M., Ohmi, T.: Quantum Computing: from Linear Algebra to Physical Realizations. CRC Press, Boca Raton (2008)

    Book  Google Scholar 

  9. Whitney, M., et al.: Automated generation of layout and control for quantum circuits. In: Proceeding of Computing, Frontiers, pp. 83–94 (2007)

  10. Alpert, C. J., Chu, C.: Physical synthesis comes of age. In: Proceedings of International Conference on Computer-Aided Design (ICCAD), pp. 246–249 (2007)

  11. Mohammadzadeh, N., Saheb Zamani, M., Sedighi, M.: Auxiliary qubit selection: a physical synthesis technique for quantum circuits. Quantum Inf. Process. 10(2), 139–154 (2011)

    Article  MathSciNet  Google Scholar 

  12. Mohammadzadeh, N., Sedighi, M., Saheb Zamani, M.: Quantum physical synthesis: improving physical design by netlist modifications. Microelectronics J. 41(4), 219–230 (2010)

    Article  Google Scholar 

  13. Balensiefer, S., Kreger-Stickles, L., Oskin, M.: QUALE: quantum architecture layout evaluator. In: Proceedings of SPIE the International Society for Optical Engineering, vol. 5815, pp. 103–114 (2005)

  14. Balensiefer, S., Kregor-Stickles, L., Oskin, M.: An evaluation framework and instruction set architecture for ion-trap based quantum micro-architectures. In: Proceedings of International Symposium on Computer Architecture (ISCA), pp. 186–196 (2005)

  15. Omer, B.: Quantum Programming in QCL. Technical University of Vienna, Master thesis (2000)

  16. Yang, T., Gerasoulis, A.: List scheduling with and without communication delays. J. Parallel Comput. 19(12), 1321–1344 (1993)

    Article  MATH  Google Scholar 

  17. Svore, K., et al.: A layered software architecture for quantum computing design tools. Computer 39(1), 74–83 (2006)

    Article  Google Scholar 

  18. Svore, K. et al.: Toward a software architecture for quantum computing design tools. In: Proceedings of the \(2^{{\rm nd}}\) International Workshop on Quantum Programming Languages (QPL), pp. 145–162 (2004)

  19. Dousti, M.J., Pedram, M.: Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric. In: Proceedings of Design, Automation, and Test in Europe (DATE), pp. 840–843 (2012)

  20. Copsey, D.E.: Designing Scalable Quantum Computer Architectures: Layout and Initialization. PH.D. Thesis, University Of California, (2005)

  21. Metodi, T. et al.: Scheduling physical operations in a quantum information processor. In: Proceedings of SPIE Defense and Security, Symposium, vol. 6244, pp. 62440T.1–62440T.12 (2006)

  22. Metodi, T., et al.: A quantum logic array microarchitecture: scalable quantum data movement and computation. In: Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pp. 305–318 (2005)

  23. Thaker, D. et al.: Quantum memory hierarchies: efficient designs to match available parallelism in quantum computing. In: Proceedings of the 33rd International Symposium on Computer Architecture (ISCA), pp. 378–390 (2006)

  24. Aqua Group: http://aqua.sfc.wide.ad.jp/index.html (2012). Accessed 25 May 2012

  25. Yamamoto Group: http://www.stanford.edu/group/yamamotogroup/index.html (2012). Accessed 25 May 2012

  26. Choi, B.S., Meter, R. V.: An \(\Theta (\sqrt{n})\)-depth quantum adder on a 2D NTC quantum computer architecture. ACM J. Emerg. Technol. Comput. Syst. 8(3), 1–22 (2012)

  27. Meter, R.V., Ladd, T.D., Fowler, A.G., Yamamoto, Y.: Distributed quantum computation architecture using semiconductor nanophotonics. Int. J. Quantum Inf. 8(2), 295–323 (2010)

    Article  Google Scholar 

  28. Jones, C., et al.: A layered architecture for quantum computing using optically-controlled quantum dots. In: 10th Asian Conference on Quantum Information Science (AQIS) (2010)

  29. Meter, R.V., Touch, J., Horsman, C.: Recursive quantum repeater networks. Prog. Inf. 8, 65–79 (2011)

    Article  Google Scholar 

  30. Meter, R.V., Ladd, T.D., Munro, W.J., Nemoto, K.: System design for a long-line quantum repeater. IEEE/ACM Trans. Netw. 17(3), 1002–1013 (2009)

    Article  Google Scholar 

  31. Fowler, A.G., Wang, D.S., Ladd, T.D., Meter, R.V., Hollenberg, L.C.: Surface code quantum communication. Phys. Rev. Lett. 104, 180503 (2010)

    Article  ADS  Google Scholar 

  32. Quantum optics Group: http://lukin.physics.harvard.edu/index.htm (2012). Accessed 25 May 2012

  33. Rabl, P.: Hybrid quantum processors: molecular ensembles as quantum memory for solid state circuits. Phys. Rev. Lett. 97, 033003 (2006)

    Article  ADS  Google Scholar 

  34. Taylor, J.M., et al.: Fault-tolerant architecture for quantum computation using electrically controlled semiconductor spins. Nat. Phys. 1, 177–183 (2005)

    Article  Google Scholar 

  35. Jiang, L.: Towards Scalable Quantum Communication and Computation: Novel Approaches and Realizations. Ph.D. Thesis, Harvard University, (2009)

  36. Duan, L.M., Lukin, M.D., Cirac, J.I., Zoller, P.: Long-distance quantum communication with atomic ensembles and linear optics. Nature 414, 413–418 (2001)

    Article  ADS  Google Scholar 

  37. Childress, J.M., Taylor, J.M., Sorensen, A.S., Lukin, M.D.: Fault-tolerant quantum communication based on solid-state photon emitters. Phys. Rev. Lett. 96, 070504 (2006)

    Article  ADS  Google Scholar 

  38. Taylor, J.: Hyperfine Interactions and Quantum Information Processing in Quantum Dots. Ph.D. Thesis, Harvard University, (2006)

  39. Mohammadzadeh, N., Sedighi, M., Saheb Zamani, M.: Gate location changing: an optimization technique for quantum circuits. Int. J. Quantum Inf. 10(3), 1250037–1–1250037–20 (2012)

    Article  Google Scholar 

  40. Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Computation. Cambridge University Press, Cambridge (2010)

    Book  MATH  Google Scholar 

  41. Barenco, A., et al.: Elementary gates for quantum computation. Phys. Rev. A 52, 3457–3467 (1995)

    Article  ADS  Google Scholar 

  42. Maslov, D., Dueck, G.W., Miller, D.M., Negrevergne, C.: Quantum circuit simplification and level compaction. IEEE Trans. CAD 27(3), 436–444 (2008)

    Article  Google Scholar 

  43. Häffner, H., Roos, C.F., Blatt, R.: Quantum computing with trapped ions. Phys. Rep. 469, 155–203 (2008)

    Google Scholar 

  44. Kielpinski, D., Monroe, C., Wineland, D.: Architecture for a large-scale ion-trap quantum computer. Nature 417, 709–711 (2002)

    Article  ADS  Google Scholar 

  45. Kim, J., et al.: System design for large-scale ion trap quantum information processor. J. Quantum Inf. Comput. 5(7), 515–537 (2005)

    MATH  Google Scholar 

  46. Hucul, D., et al.: On the transport of atomic ions in linear and multidimensional ion trap arrays. J. Quantum Inf. Comput. 8(6), 0501–0578 (2008)

    MathSciNet  Google Scholar 

  47. Chiaverini, J., et al.: Surface-electrode architecture for ion-trap quantum information processing. J. Quantum Inf. Comput. 5(5), 419–439 (2005)

    MathSciNet  MATH  Google Scholar 

  48. Whitney, M., et al.: A Fault Tolerant, Area Efficient Architecture for Shor’s Factoring Algorithm. ISCA’09, pp. 383–394 (2009)

  49. Isailovic, N.: An Investigation into the Realities of a Quantum Datapath. University of California at Berkeley, Technical Report (2010)

  50. Maslov, D., Dueck, G.W.: Improved quantum cost for n-bit Toffoli gates. IEE Electron. Lett. 39(25), 1790–1791 (2003)

    Article  Google Scholar 

  51. Cross, A.: Synthesis and Evaluation of Fault-Tolerant Quantum Computer Architectures. Ph.D. Thesis, Massachusetts Institute of Technology, (2005)

  52. Maslov, D., Dueck, G., Scott, N.: Reversible Logic Synthesis Benchmarks Page. http://www.cs.uvic.ca/dmaslov/

  53. Robert, W., et al.: Quiver: An Online Tool for Reversible Quantum Circuit Visualization and Verification. http://www.revlib.org/tools.php (2012). Accessed 25 March 2012

  54. IBM Rational Software, Version 2003: www.ibm.com/software/rational (2012). Accessed 25 March 2012

  55. Khan, M.H., Perkowski, M.A., Kerntopf, P.: Multi-output Galois field sum of products synthesis with new quantum cascades. In: Proceedings of the \(33^{{\rm rd}}\) International Symposium on Multiple-Valued Logic (ISMVL), pp. 146–153 (2003)

Download references

Acknowledgments

We would like to thank Prof. Wineland and Prof. Kubiatowicz for their invaluable deliberations.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Naser Mohammadzadeh.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Mohammadzadeh, N., Saheb Zamani, M. & Sedighi, M. Quantum circuit physical design methodology with emphasis on physical synthesis. Quantum Inf Process 13, 445–465 (2014). https://doi.org/10.1007/s11128-013-0661-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11128-013-0661-2

Keywords