Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

Advertisement

Springer Nature Link
Log in

A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

Network-on-chip-based communication schemes represent a promising solution to the increasing complexity of system-on-chip problems. In this paper, we propose a new mesh-like topology called the shortly connected mesh technology (ScMesh), which is based on the traditional mesh topology, to exploit the graph symmetry properties of interconnection networks. This proposed topology not only enhances network performance by reducing the network diameter, but also provides a lower area/energy solution for interconnection network scenarios. This study analyzes and compares the performance of ScMesh to some newly improved topologies, including the WK-recursive, extended-butterfly fat tree, and diametrical mesh topologies. The experiment results indicate that ScMesh outperforms the other topologies, with throughput increases of 47.71, 33.45, and 18.64 % as well as latency decreases of 45.71, 35.84, and 14.58 % compared to the extended-butterfly fat tree, WK-recursive and diametrical mesh topologies, respectively. In addition, ScMesh achieves 41.22, 32.23, and 15.01 % lower energy consumption and 38.96, 27.43, and 18.21 % lower area overhead than the extended-butterfly fat tree, WK-recursive, and diametrical mesh topologies, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20

Similar content being viewed by others

References

  1. Chang KC (2011) Reliable network-on-chip design for multi-core system-on-chip. J Supercomput 55(1):86–102

    Article  Google Scholar 

  2. Lecler JJ, Baillieu G (2011) Application driven network-on-chip architecture exploration and refinement for a complex SoC. Des. Autom Embedded Syst 15(2):133–158

    Article  Google Scholar 

  3. Chung H, Teuscher C (2013) Design and analysis of heterogenous nanoscale on-chip communication networks. Nano Commun Netw 4(1):23–42

    Article  Google Scholar 

  4. Kumar S, Jantsch A, Soininen JP, Forsell M, Millberg M, Oberg J, Tiensyrja K, Hemani A (2002) A network-on-chip architecture and design methodology. In: Proceedings of IEEE Annual Symposium Computer Society, VLSI, pp 105–112

  5. Guerrier P, Greiner A (2000) A generic architecture for on-chip packet-switched interconnections. In: Proceedings of IEEE Design Automation Test Europe Conference, pp 250–256

  6. Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceedings of IEEE Design Automation Test Europe Conference, pp 684–689

  7. Karim F, Nguyen A, Dey S (2002) An interconnect architecture for networking systems on chips. IEEE Micro 22(5):36–45

    Article  Google Scholar 

  8. Hossain H, Akbar MM, Islam MM (2005) Extended-butterfly fat tree interconnection (EFTI) architecture for network-on-chip. In: Proceedings of IEEE PACRIM on Communications, Computers and Signal Processing, pp 613–616

  9. Ghosal P, Das TS (2013) A novel routing algorithm for on-chip communication in NoC on diametrical 2D mesh interconnection architecture. Adv Intell Syst Comput 178:667–676

    Article  Google Scholar 

  10. Suboh S, Bakhouya M, Gaber J, Ghazawi TE (2008) An interconnection architecture for network-on-chip systems. J Telecommun Syst 37(1):137–144

    Article  Google Scholar 

  11. Seifi MR, Eshghi M (2012) Clustered NoC, a suitable design for group communications in network-on-chip. J Comput Electr Eng 38(1):82–95

    Article  Google Scholar 

  12. Kotsis G (1992) Interconnection topologies and routing for parallel processing systems. http://www.tk.uni-linz.ac.at/download/papers/gk_dipl.pdf

  13. Lin J, Lin X (2012) Power and latency efficient mechanism: a seamless bridge between buffered and bufferless routing in on-chip network. J Supercomput 61(3):1048–1067

    Article  Google Scholar 

  14. Fang JF, Wang YR, Huang HL (2007) The m-panacycle-connectivity of a WK-Recursive network. J Inform Sci 177:5611–5619

    Article  MATH  MathSciNet  Google Scholar 

  15. Camacho J, Flich J, Duato J, Eberle H, Olesinski W (2011) A power-efficient network-on-chip topology. In: Proceedings of 5th International Workshop on Interconnection Network, Architecture, pp 23–26

  16. Nadooshan SR, Modarressi M, Azad SH (2012) The 2D digraph-based NoCs: attractive alernatives to the 2D mesh NoCs. J Supercomput 59(1):1–21

    Article  Google Scholar 

  17. Orgas UY, Marculescu R (2006) It’s a small world after all: NoC performance optimization via long-range link insertion. IEEE Trans VLSI Syst 14(7):693–706

    Article  Google Scholar 

  18. Joshi A, Byungsub K, Stojanovic V (2009) Designing energy-efficient low-diameter on-chip networks with equalized interconnects. In: 17th IEEE Symposium on High Performance Interconnects, pp 3–12

  19. Holsmark R, Palesi M, Kumar S (2008) Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions. J Syst Archit 54(3):427–440

    Article  Google Scholar 

  20. Mubeen S (2009) Evaluation of source routing for mesh topology network-on-chip platforms. Dissertation, University of Jonkoping

  21. Deorio A, Fick D, Bertacco V, Sylvester D, Blaauw D, Jin H, Chen G (2012) A reliable routing architecture and algorithm for NoCs. IEEE Trans Comput Aided Des Integr Circuits Syst 31(5):726–739

    Article  Google Scholar 

  22. Dally WJ, Seitz CL (1987) Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans Comput C 36(5):547–553

    Article  MATH  Google Scholar 

  23. Glass CJ, Ni LM (1992) The turn model for adaptive routing. In: Proceedings of 19th IEEE International Symposium on Computer Architecture, pp 278–287

  24. Pande PP, Grecu C, Jones M, Ivanov A, Saleh R (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54(8):1025–1040

    Article  Google Scholar 

  25. Miligi E (2011) Networks-on-chips: modeling, analysis and design methodologies. Dissertation, University of Victoria

  26. Wang L, Song H, Jiang Y, Zhang L (2009) A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures. J Comput Electr Eng 35(6):846–855

    Article  MATH  Google Scholar 

  27. Ye TT, Benini L, Micheli GD (2002) Analysis of power consumption on switch fabrics in network routers. In: Proceedings of IEEE Design Automation Conference, pp 524–529

  28. Bakhouya M (2009) Evaluating the energy consumption and the silicon area of on-chip interconnect architectures. J Syst Archit 55(7):387–395

    Article  Google Scholar 

  29. Abd-El-Barr M, Al-Somani TF (2011) Topological properties of hierarchical interconnection networks: a review and comparison. J Electr Comput Eng. 2011:12 doi:10.1155/2011/189434

  30. Camarero C, Martinez C, Beivide R (2012) L-networks: a topological model for regular two-dimensional interconnection networks. Comput IEEE Trans. 62(7):1362–1375 doi:10.1109/TC.2012.77

    Google Scholar 

  31. Ghany MAE, Moursy MAE, Ismail M (2009) High throughput architecture for high performance NoC. In: Proceedings of IEEE International Symposium on Circuits and Systems, pp 2241–2244

  32. Lu Z, Thid R, Millberg M, Nilsson E, Jantsch A (2005) NNSE: nostrum network-on-chip simulation environment. In: Proceedings of International Conference on Swedish System-on-Chip

  33. Fazzino F, Palesi M, Patti D (2006) Noxim: network-on-chip simulator. http://noxim.sourceforge.net

  34. Azimi A, Ahrabi A, Bahrbegi H, Bahrbegi M (2009) Gpnocsim++: a network-on-chip simulator. http://www.sourceforge.net/projects/gpnocsimpp

  35. Varatkar G, Marculescu R (2002) Traffic analysis for on-chip networks design of multimedia applications. In: Proceedings of 39th IEEE Design Automation Conference, pp 795–800

  36. Zhonghai L, Jantsch A (2005) Traffic configuration for evaluating networks on chips. In: Proceedings of 5th IEEE International Workshop on System-on-Chip for Real-Time Applications, pp 535–540

  37. Kahng AB, Bin L, Shiuan PL, Samadi K (2012) ORION 2.0: a power-area simulator for interconnection networks. IEEE Trans VLSI Syst 20(1):191–196

    Article  Google Scholar 

  38. Dally WJ, Towles B (2004) Principle and practices of interconnection networks. Morgan Kaufmann, Massachusetts

    Google Scholar 

  39. Sheibanyrad A (2010) 3D integration for NoC-based SoC architecture. Springer Verlag, Berlin

    Google Scholar 

Download references

Acknowledgments

This work was supported by a National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No. NRF-2013R1A2A2A05004566).

Author information

Author notes

  1. Jong-Myon Kim

    Present address: School of Electrical Engineering, University of Ulsan, Bldg. #7, Room #308, 93 Daehak-ro Mugeo-dong Nam-gu, Ulsan , 680-749, South Korea

Authors and Affiliations

  1. School of Electrical Engineering, University of Ulsan, Ulsan, South Korea

    Md. Hasan Furhad

Authors
  1. Md. Hasan Furhad
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jong-Myon Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jong-Myon Kim.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Furhad, M.H., Kim, JM. A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures. J Supercomput 69, 766–792 (2014). https://doi.org/10.1007/s11227-014-1178-x

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-014-1178-x

Keywords

Search

Navigation