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Multi-cache resizing via greedy coordinate descent

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Abstract

To reduce power consumption in CPUs, researchers have studied dynamic cache resizing. However, existing techniques only resize a single cache within a uniprocessor or the shared last-level cache (LLC) within a multi-core CPU. To maximize benefits, it is necessary to resize all caches, which in today’s CPUs includes one or two private caches per core and a shared LLC. Such multi-cache resizing (MCR) is challenging, because the multiple resizing decisions are coupled, yielding an enormous configuration space. In this paper, we present a dynamic MCR technique that uses search-based optimization. Our main contribution is a set of heuristics that enable the search to find the best configuration rapidly. In particular, our search moves in a coordinate descent (Manhattan) fashion across the configuration space. At each search step, we select the next cache for resizing greedily based on a power efficiency gain metric. To further enhance search speed, we permit parallel greedy selection. Across 60 multi-programmed workloads, our technique reduces power by 13.9% while sacrificing 1.5% of the performance.

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Notes

  1. Simple compounding yields 768\(^{2}\), 1536\(^{4}\), and 3072\(^{8}\) configurations for 2-, 4-, and 8-core CPUs, but many of these are infeasible, since the limited LLC capacity is shared across the simultaneous benchmarks.

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Acknowledgements

Funding was provided by the National Science Foundation (Grant No. CCF-1117042) and the Defense Advanced Research Projects Agency (Grant No. HR0011-13-2-0005).

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Authors and Affiliations

  1. Samsung, 3655 N 1st Street, San Jose, CA, 95134, USA

    I. Stephen Choi

  2. University of Maryland at College Park, 1323 A. V. Williams, College Park, MD, 20742, USA

    Donald Yeung

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  1. I. Stephen Choi
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Correspondence to Donald Yeung.

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Choi, I.S., Yeung, D. Multi-cache resizing via greedy coordinate descent. J Supercomput 73, 2402–2429 (2017). https://doi.org/10.1007/s11227-016-1927-0

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