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SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU–GPU heterogeneous architectures

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Abstract

Shared last-level cache (LLC) in on-chip CPU–GPU heterogeneous architectures is critical to the overall system performance, since CPU and GPU applications usually show completely different characteristics on cache accesses. Therefore, when co-running with CPU applications, GPU ones can easily occupy the majority of the LLC, making CPU applications starve severely. This imposes significant challenges to the design and management of the shared LLC in CPU–GPU heterogeneous architectures. To improve the overall system performance, we consider integrating conventional SRAM and a new memory technology (i.e., STT-RAM) to enlarge the shared LLC. Furthermore, we propose comprehensive management policies to reduce the contention between CPU and GPU units. Experimental results show that, compared with the conventional SRAM-only LLC design, our proposal improves the performance of CPU workloads by 17% while not hurting GPU ones and reduces the LLC energy consumption by 30% on average.

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Acknowledgements

This work was supported in part by National Key R&D Program of China Nos. 2017YFB0203201 and 2017YFC0820100 and by NSFC Nos. 61732002 and 61202425. We thank all reviewers for their valuable comments and advice on improving this paper.

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Authors and Affiliations

  1. School of Computer Science and Engineering, Beihang University, Beijing, China

    Lan Gao, Rui Wang, Hailong Yang, Zhongzhi Luan & Depei Qian

  2. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

    Yunlong Xu

  3. Beijing Simulation Center, Beijing, China

    Han Zhang & Jihong Cai

Authors
  1. Lan Gao
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  2. Rui Wang
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  3. Yunlong Xu
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  4. Hailong Yang
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  7. Han Zhang
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Correspondence to Rui Wang.

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Gao, L., Wang, R., Xu, Y. et al. SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU–GPU heterogeneous architectures. J Supercomput 74, 3388–3414 (2018). https://doi.org/10.1007/s11227-018-2389-3

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